[Intel-xe] [PATCH] drm/xe: Fix WA 14010918519 write to wrong register

[Gustavo Sousa]

Quoting Lucas De Marchi (2023-10-24 19:04:12-03:00)
>FORCE_SLM_FENCE_SCOPE_TO_TILE and FORCE_UGM_FENCE_SCOPE_TO_TILE are in
>the up dword of LSC_CHICKEN_BIT_0 register. Also, the 14010918519
>workaround only applies to early steppings, A*. Eventually those should
>be dropped, like they were in commit eaeb4b361452 ("drm/i915/dg2: Drop
>pre-production GT workarounds"), so let's make sure they are annotated
>appropriately.
>
>Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

>---
> drivers/gpu/drm/xe/xe_wa.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>index 1450af6cab34..b4b13d05ef26 100644
>--- a/drivers/gpu/drm/xe/xe_wa.c
>+++ b/drivers/gpu/drm/xe/xe_wa.c
>@@ -352,9 +352,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>           XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
>         },
>         { XE_RTP_NAME("14010918519"),
>-          XE_RTP_RULES(SUBPLATFORM(DG2, G10),
>+          XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
>                        FUNC(xe_rtp_match_first_render_or_compute)),
>-          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0,
>+          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
>                              FORCE_SLM_FENCE_SCOPE_TO_TILE |
>                              FORCE_UGM_FENCE_SCOPE_TO_TILE,
>                              /*
>-- 
>2.40.1
>