[Intel-xe] ✓ CI.Patch_applied: success for Refactor VM bind code
Patchwork
patchwork at emeril.freedesktop.org
Thu Oct 26 04:51:06 UTC 2023
== Series Details ==
Series: Refactor VM bind code
URL : https://patchwork.freedesktop.org/series/125608/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 4c7ed0ef2 drm/xe/mocs: MOCS registers are multicast on Xe_HP and beyond
=== git am output follows ===
Applying: drm/xe: Allow num_binds == 0 in VM bind IOCTL
Applying: drm/xe: Allow num_batch_buffer == 0 in exec IOCTL
Applying: drm/xe: Lock all gpuva ops during VM bind IOCTL
Applying: drm/xe: Add ops_execute function which returns a fence
Applying: drm/xe: Move migrate to prefetch to op_lock funtion
Applying: drm/xe: Add struct xe_vma_ops abstraction
Applying: drm/xe: Update xe_vm_rebind to use dummy VMA operations
Applying: drm/xe: Move drm exec loop to vm_bind_ioctl_ops_execute
Applying: drm/xe: Fixup error handling / ref counting in VM bind IOCTL
Applying: drm/xe: Convert pagefault rebind to use ops interface
Applying: drm/xe: Add some members to xe_vma_ops
Applying: drm/xe: Add vm_bind_ioctl_ops_install_fences helper
Applying: drm/xe: Drop rebind argument from xe_pt_prepare_bind
Applying: drm/xe: Add xe_vm_pgtable_update_op to xe_vma_ops
Applying: drm/xe: Move setting last fence and sync wait to vm_bind_ioctl_ops_install_fences
Applying: drm/xe: Fix vma_is_valid to use tile argument
Applying: drm/xe: Adjust tile mask in operations create
Applying: drm/xe: Add xe_gt_tlb_invalidation_range and convert PT layer to use this
Applying: drm/xe: s/xe_tile_migrate_engine/xe_tile_migrate_exec_queue
Applying: drm/xe: Convert multiple bind ops into single job
Applying: drm/xe: Update clear / populate arguments
Applying: drm/xe: Add __xe_migrate_update_pgtables_cpu helper
Applying: drm/xe: Add xe_hw_fence_signal helper
Applying: drm/xe: CPU binds for jobs
Applying: drm/xe: Don't use migrate exec queue for page fault binds
Applying: drm/xe/uapi: Make sync vs async VM bind operations per IOCTL rather than queue
More information about the Intel-xe
mailing list