[Intel-xe] ✗ CI.checkpatch: warning for Fix LRC workarounds

[Patchwork]

== Series Details ==

Series: Fix LRC workarounds
URL   : https://patchwork.freedesktop.org/series/123286/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
e700ea2f248a75138759bcb443affeef4a2d1991
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e527ded4175e5a1365f05f644e4107d11b6fc90d
Author: Lucas De Marchi <lucas.demarchi at intel.com>
Date:   Tue Sep 5 07:31:44 2023 -0700

    drm/xe: Fix LRC workarounds
    
    Fix 2 issues when writing LRC workarounds by copying the same handling
    done when processing other RTP entries:
    
    For masked registers, it was not correctly setting the upper 16bits.
    Differently than i915, the entry itself doesn't set the upper bits
    for masked registers: this is done when applying them. Testing on ADL-P:
    
    Before:
            [drm:xe_gt_record_default_lrcs [xe]] LRC WA rcs0 save-restore MMIOs
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x2580] = 0x00000002
            ...
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x7018] = 0x00002000
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x7300] = 0x00000040
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x7304] = 0x00000200
    
    After:
            [drm:xe_gt_record_default_lrcs [xe]] LRC WA rcs0 save-restore MMIOs
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x2580] = 0x00060002
            ...
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x7018] = 0x20002000
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x7300] = 0x00400040
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x7304] = 0x02000200
    
    All of these registers are masked registers, so writing to them without
    the relevant bits in the upper 16b doesn't have any effect.
    
    Also, this adds support to regular registers; previously it was assumed
    that LRC entries would only contain masked registers. However this is
    not true. 0x6604 is not a masked register, but used in workarounds for
    e.g.  ADL-P. See commit 28cf243a341a ("drm/i915/gt: Fix context
    workarounds with non-masked regs"). In the same test with ADL-P as
    above:
    
    Before:
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x6604] = 0xe0000000
    After:
            [drm:xe_gt_record_default_lrcs [xe]] REG[0x6604] = 0xe0efef6f
    
    As can be seen, now it will read what was in the register rather than
    completely overwrite the other bits.
    
    Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
+ /mt/dim checkpatch 7ec520d3a63b6e95174329108cd44359a70907ba drm-intel
/mt/dim: line 50: /root/.dimrc: No such file or directory