[Intel-xe] [PATCH 0/6] MMIO extension support for multi-tile devices

[Koby Elbaz]

By design, the Xe driver supports the same contiguous MMIO address space
for all Intel GPU devices - 16MB (hard-coded) per tile.
However, in future devices, there will be an additional contiguous multi-
tile (up to 256M per tile) MMIO extension space ON TOP of it, and hence
the necessity for the MMIO extension support.
The 1st patch in this patchset updates 'struct xe_reg' to support 28-bit
address representation in order to access larger MMIO spaces.
While the other patches essentially divide the mapped MMIO BAR into the
MMIO space and the additional, per-tile, MMIO extension space.

Koby Elbaz (6):
  drm/xe: add 28-bit address support in struct xe_reg
  drm/xe: add read/write support for MMIO extension space
  drm/xe: add a flag to bypass multi-tile config from MTCFG reg
  drm/xe: add MMIO extension support flags
  drm/xe: map MMIO BAR according to the num of tiles in device desc
  drm/xe: refactor xe_mmio_probe_tiles to support MMIO extension

 drivers/gpu/drm/xe/regs/xe_reg_defs.h | 16 +++++-
 drivers/gpu/drm/xe/xe_device_types.h  | 19 +++++++
 drivers/gpu/drm/xe/xe_mmio.c          | 79 ++++++++++++++-------------
 drivers/gpu/drm/xe/xe_mmio.h          |  8 +--
 drivers/gpu/drm/xe/xe_pci.c           |  5 ++
 drivers/gpu/drm/xe/xe_pci_types.h     |  2 +
 6 files changed, 85 insertions(+), 44 deletions(-)

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2.34.1