[Intel-xe] [PATCH 6/6] fixup! drm/xe/display: Implement display support
Matt Roper
matthew.d.roper at intel.com
Wed Sep 13 23:14:18 UTC 2023
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
drivers/gpu/drm/xe/Makefile | 4 +-
.../drm/xe/display/ext/intel_clock_gating.c | 124 ------------------
drivers/gpu/drm/xe/xe_display.c | 2 -
3 files changed, 2 insertions(+), 128 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/display/ext/intel_clock_gating.c
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 9d2311f8141f..bcfa7daf7303 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -147,8 +147,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/xe_plane_initial.o \
display/xe_display_rps.o \
display/ext/i915_irq.o \
- display/ext/i915_utils.o \
- display/ext/intel_clock_gating.o
+ display/ext/i915_utils.o
# SOC code shared with i915
xe-$(CONFIG_DRM_XE_DISPLAY) += \
@@ -183,6 +182,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
i915-display/intel_display_power_map.o \
i915-display/intel_display_power_well.o \
i915-display/intel_display_trace.o \
+ i915-display/intel_display_wa.o \
i915-display/intel_dkl_phy.o \
i915-display/intel_dmc.o \
i915-display/intel_dp.o \
diff --git a/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c b/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c
deleted file mode 100644
index 88b1aee0351f..000000000000
--- a/drivers/gpu/drm/xe/display/ext/intel_clock_gating.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Eugeni Dodonov <eugeni.dodonov at intel.com>
- *
- */
-
-#include "intel_de.h"
-#include "intel_display_trace.h"
-
-#include "i915_drv.h"
-#include "i915_reg.h"
-#include "intel_clock_gating.h"
-#include "intel_mchbar_regs.h"
-
-static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- /* Wa_1409120013 */
- if (DISPLAY_VER(dev_priv) == 12)
- intel_de_write(dev_priv, ILK_DPFC_CHICKEN(INTEL_FBC_A),
- DPFC_CHICKEN_COMP_DUMMY_PIXEL);
-
- /* Wa_1409825376:tgl (pre-prod)*/
- if (IS_TIGERLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
- intel_de_write(dev_priv, GEN9_CLKGATE_DIS_3, intel_de_read(dev_priv, GEN9_CLKGATE_DIS_3) |
- TGL_VRH_GATING_DIS);
-
- /* Wa_14013723622:tgl,rkl,dg1,adl-s */
- if (DISPLAY_VER(dev_priv) == 12)
- intel_de_rmw(dev_priv, CLKREQ_POLICY,
- CLKREQ_POLICY_MEM_UP_OVRD, 0);
-}
-
-static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- gen12lp_init_clock_gating(dev_priv);
-
- /* Wa_22011091694:adlp */
- intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
-
- /* Bspec/49189 Initialize Sequence */
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
-}
-
-static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- gen12lp_init_clock_gating(dev_priv);
-
- /* Wa_1409836686:dg1[a0] */
- if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_write(dev_priv, GEN9_CLKGATE_DIS_3, intel_de_read(dev_priv, GEN9_CLKGATE_DIS_3) |
- DPT_GATING_DIS);
-}
-
-static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- /* Wa_22010146351:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
-}
-
-static void dg2_init_clock_gating(struct drm_i915_private *i915)
-{
- /* Wa_22010954014:dg2 */
- intel_de_rmw(i915, XEHP_CLOCK_GATE_DIS, 0,
- SGSI_SIDECLK_DIS);
-
- /*
- * Wa_14010733611:dg2_g10
- * Wa_22010146351:dg2_g10
- */
- if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0))
- intel_de_rmw(i915, XEHP_CLOCK_GATE_DIS, 0,
- SGR_DIS | SGGI_DIS);
-}
-
-static void pvc_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- /* Wa_14012385139:pvc */
- if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
-
- /* Wa_22010954014:pvc */
- if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
-}
-
-void intel_clock_gating_init(struct drm_i915_private *dev_priv)
-{
- if (IS_PONTEVECCHIO(dev_priv))
- pvc_init_clock_gating(dev_priv);
- else if (IS_DG2(dev_priv))
- dg2_init_clock_gating(dev_priv);
- else if (IS_XEHPSDV(dev_priv))
- xehpsdv_init_clock_gating(dev_priv);
- else if (IS_ALDERLAKE_P(dev_priv))
- adlp_init_clock_gating(dev_priv);
- else if (IS_DG1(dev_priv))
- dg1_init_clock_gating(dev_priv);
- else if (GRAPHICS_VER(dev_priv) == 12)
- gen12lp_init_clock_gating(dev_priv);
- else
- MISSING_CASE(INTEL_DEVID(dev_priv));
-}
diff --git a/drivers/gpu/drm/xe/xe_display.c b/drivers/gpu/drm/xe/xe_display.c
index 0b569b229ab1..ffaaacc72c54 100644
--- a/drivers/gpu/drm/xe/xe_display.c
+++ b/drivers/gpu/drm/xe/xe_display.c
@@ -18,7 +18,6 @@
#include "intel_acpi.h"
#include "intel_audio.h"
#include "intel_bw.h"
-#include "intel_clock_gating.h"
#include "intel_display.h"
#include "intel_display_driver.h"
#include "intel_display_irq.h"
@@ -399,7 +398,6 @@ void xe_display_pm_resume(struct xe_device *xe)
drm_mode_config_reset(&xe->drm);
intel_display_driver_init_hw(xe);
- intel_clock_gating_init(xe);
intel_hpd_init(xe);
/* MST sideband requires HPD interrupts enabled */
--
2.41.0
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