[Intel-xe] [PATCH v2 2/6] drm/xe: move pat_table into device info
Matt Roper
matthew.d.roper at intel.com
Thu Sep 14 23:53:48 UTC 2023
On Thu, Sep 14, 2023 at 04:31:15PM +0100, Matthew Auld wrote:
> We need to able to know the max pat_index range for a given platform, as
> well being able to lookup the pat_index for a given platform in upcoming
> vm_bind uapi, where userspace can directly provide the pat_index. Move
> the platform definition of the pat_table into the device info with the
> idea of encoding more information about each pat_index in a future
> patch.
>
> v2 (Lucas):
> - s/ENODEV/ENOTSUPP/
> - s/xe_pat_fill_info/xe_pat_init_early/
> - Prefer new pat substruct in xe_info.
>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Pallavi Mishra <pallavi.mishra at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 11 ++++++++
> drivers/gpu/drm/xe/xe_pat.c | 39 ++++++++++++++++++----------
> drivers/gpu/drm/xe/xe_pat.h | 1 +
> drivers/gpu/drm/xe/xe_pci.c | 7 +++++
> 4 files changed, 44 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 5037b8c180b8..6c50d0f03466 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -238,6 +238,17 @@ struct xe_device {
> /** @enable_display: display enabled */
> u8 enable_display:1;
>
> + /** @pat: Platform information related to PAT settings. */
For the top-level comment here we may want to write out "Page Attribute
Table" once.
> + struct {
> + /**
> + * @table: The PAT table encoding for every pat_index
> + * supported by the platform.
> + */
> + const u32 *table;
We should probably have a space between these two fields for
readability.
Aside from those minor tweaks,
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> + /** @n_entries: The number of entries in the @table */
> + int n_entries;
> + } pat;
> +
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> const struct intel_display_device_info *display;
> struct intel_display_runtime_info display_runtime;
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 32b0c922e7fa..aa2c5eb88266 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -106,24 +106,17 @@ static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
> }
> }
>
> -void xe_pat_init(struct xe_gt *gt)
> +int xe_pat_init_early(struct xe_device *xe)
> {
> - struct xe_device *xe = gt_to_xe(gt);
> -
> if (xe->info.platform == XE_METEORLAKE) {
> - /*
> - * SAMedia register offsets are adjusted by the write methods
> - * and they target registers that are not MCR, while for normal
> - * GT they are MCR
> - */
> - if (xe_gt_is_media_type(gt))
> - program_pat(gt, mtl_pat_table, ARRAY_SIZE(mtl_pat_table));
> - else
> - program_pat_mcr(gt, mtl_pat_table, ARRAY_SIZE(mtl_pat_table));
> + xe->info.pat.table = mtl_pat_table;
> + xe->info.pat.n_entries = ARRAY_SIZE(mtl_pat_table);
> } else if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2) {
> - program_pat_mcr(gt, pvc_pat_table, ARRAY_SIZE(pvc_pat_table));
> + xe->info.pat.table = pvc_pat_table;
> + xe->info.pat.n_entries = ARRAY_SIZE(pvc_pat_table);
> } else if (GRAPHICS_VERx100(xe) <= 1210) {
> - program_pat(gt, tgl_pat_table, ARRAY_SIZE(tgl_pat_table));
> + xe->info.pat.table = tgl_pat_table;
> + xe->info.pat.n_entries = ARRAY_SIZE(tgl_pat_table);
> } else {
> /*
> * Going forward we expect to need new PAT settings for most
> @@ -135,7 +128,25 @@ void xe_pat_init(struct xe_gt *gt)
> */
> drm_err(&xe->drm, "Missing PAT table for platform with graphics version %d.%02d!\n",
> GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);
> + return -ENOTSUPP;
> }
> +
> + return 0;
> +}
> +
> +void xe_pat_init(struct xe_gt *gt)
> +{
> + struct xe_device *xe = gt_to_xe(gt);
> +
> + /*
> + * SAMedia register offsets are adjusted by the write methods
> + * and they target registers that are not MCR, while for normal
> + * GT they are MCR.
> + */
> + if (xe_gt_is_media_type(gt) || GRAPHICS_VERx100(xe) < 1255)
> + program_pat(gt, xe->info.pat.table, xe->info.pat.n_entries);
> + else
> + program_pat_mcr(gt, xe->info.pat.table, xe->info.pat.n_entries);
> }
>
> void xe_pte_pat_init(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
> index 5e71bd98d787..2f89503233b9 100644
> --- a/drivers/gpu/drm/xe/xe_pat.h
> +++ b/drivers/gpu/drm/xe/xe_pat.h
> @@ -28,6 +28,7 @@
> struct xe_gt;
> struct xe_device;
>
> +int xe_pat_init_early(struct xe_device *xe);
> void xe_pat_init(struct xe_gt *gt);
> void xe_pte_pat_init(struct xe_device *xe);
> unsigned int xe_pat_get_index(struct xe_device *xe, enum xe_cache_level cache);
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index dc233a1226bd..2806311bd6a4 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -22,6 +22,7 @@
> #include "xe_gt.h"
> #include "xe_macros.h"
> #include "xe_module.h"
> +#include "xe_pat.h"
> #include "xe_pci_types.h"
> #include "xe_pm.h"
> #include "xe_step.h"
> @@ -531,6 +532,7 @@ static int xe_info_init(struct xe_device *xe,
> struct xe_tile *tile;
> struct xe_gt *gt;
> u8 id;
> + int err;
>
> xe->info.platform = desc->platform;
> xe->info.subplatform = subplatform_desc ?
> @@ -579,6 +581,11 @@ static int xe_info_init(struct xe_device *xe,
> xe->info.enable_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
> enable_display &&
> desc->has_display;
> +
> + err = xe_pat_init_early(xe);
> + if (err)
> + return err;
> +
> /*
> * All platforms have at least one primary GT. Any platform with media
> * version 13 or higher has an additional dedicated media GT. And
> --
> 2.41.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
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