[Intel-xe] [PATCH v2 4/6] drm/xe/pat: annotate pat_index with coherency mode
Matt Roper
matthew.d.roper at intel.com
Fri Sep 15 00:08:37 UTC 2023
On Thu, Sep 14, 2023 at 04:31:17PM +0100, Matthew Auld wrote:
> Future uapi needs to give userspace the ability to select the pat_index
> for a given vm_bind. However we need to be able to extract the coherency
> mode from the provided pat_index to ensure it matches the coherency mode
> set at object creation. There are various security reasons for why this
> matters. However the pat_index itself is very platform specific, so
> seems reasonable to annotate each platform definition of the pat table.
> On some older platforms there is no explicit coherency mode, so we just
> pick whatever makes sense.
>
> v2:
> - Simplify with COH_AT_LEAST_1_WAY
> - Add some kernel-doc
>
> Bspec: 45101, 44235 #xe
> Bspec: 70552, 71582, 59400 #xe2
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Pallavi Mishra <pallavi.mishra at intel.com>
> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Filip Hazubski <filip.hazubski at intel.com>
> Cc: Carl Zhang <carl.zhang at intel.com>
> Cc: Effie Yu <effie.yu at intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 2 +-
> drivers/gpu/drm/xe/xe_pat.c | 59 +++++++++++++++++-----------
> drivers/gpu/drm/xe/xe_pat.h | 18 +++++++++
> 3 files changed, 54 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 6c50d0f03466..959e095eb46c 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -244,7 +244,7 @@ struct xe_device {
> * @table: The PAT table encoding for every pat_index
> * supported by the platform.
> */
> - const u32 *table;
> + const struct xe_pat_table_entry *table;
> /** @n_entries: The number of entries in the @table */
> int n_entries;
> } pat;
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index fb490982fd99..f4fceb3fa086 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -4,6 +4,8 @@
> */
>
>
> +#include <drm/xe_drm.h>
> +
> #include "regs/xe_reg_defs.h"
> #include "xe_gt.h"
> #include "xe_gt_mcr.h"
> @@ -33,30 +35,30 @@
> #define TGL_PAT_WC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 1)
> #define TGL_PAT_UC REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 0)
>
> -static const u32 tgl_pat_table[] = {
> - [0] = TGL_PAT_WB,
> - [1] = TGL_PAT_WC,
> - [2] = TGL_PAT_WT,
> - [3] = TGL_PAT_UC,
> +static const struct xe_pat_table_entry tgl_pat_table[] = {
> + [0] = { TGL_PAT_WB, XE_GEM_COH_AT_LEAST_1WAY },
> + [1] = { TGL_PAT_WC, XE_GEM_COH_NONE },
> + [2] = { TGL_PAT_WT, XE_GEM_COH_NONE },
> + [3] = { TGL_PAT_UC, XE_GEM_COH_NONE },
> };
>
> -static const u32 pvc_pat_table[] = {
> - [0] = TGL_PAT_UC,
> - [1] = TGL_PAT_WC,
> - [2] = TGL_PAT_WT,
> - [3] = TGL_PAT_WB,
> - [4] = PVC_PAT_CLOS(1) | TGL_PAT_WT,
> - [5] = PVC_PAT_CLOS(1) | TGL_PAT_WB,
> - [6] = PVC_PAT_CLOS(2) | TGL_PAT_WT,
> - [7] = PVC_PAT_CLOS(2) | TGL_PAT_WB,
> +static const struct xe_pat_table_entry pvc_pat_table[] = {
> + [0] = { TGL_PAT_UC, XE_GEM_COH_NONE },
> + [1] = { TGL_PAT_WC, XE_GEM_COH_NONE },
> + [2] = { TGL_PAT_WT, XE_GEM_COH_NONE },
> + [3] = { TGL_PAT_WB, XE_GEM_COH_AT_LEAST_1WAY },
> + [4] = { PVC_PAT_CLOS(1) | TGL_PAT_WT, XE_GEM_COH_NONE },
> + [5] = { PVC_PAT_CLOS(1) | TGL_PAT_WB, XE_GEM_COH_AT_LEAST_1WAY },
> + [6] = { PVC_PAT_CLOS(2) | TGL_PAT_WT, XE_GEM_COH_NONE },
> + [7] = { PVC_PAT_CLOS(2) | TGL_PAT_WB, XE_GEM_COH_AT_LEAST_1WAY },
> };
>
> -static const u32 mtl_pat_table[] = {
> - [0] = MTL_PAT_0_WB,
> - [1] = MTL_PAT_1_WT,
> - [2] = MTL_PAT_3_UC,
> - [3] = MTL_PAT_0_WB | MTL_2_COH_1W,
> - [4] = MTL_PAT_0_WB | MTL_3_COH_2W,
> +static const struct xe_pat_table_entry mtl_pat_table[] = {
> + [0] = { MTL_PAT_0_WB, XE_GEM_COH_NONE },
> + [1] = { MTL_PAT_1_WT, XE_GEM_COH_NONE },
> + [2] = { MTL_PAT_3_UC, XE_GEM_COH_NONE },
> + [3] = { MTL_PAT_0_WB | MTL_2_COH_1W, XE_GEM_COH_AT_LEAST_1WAY },
> + [4] = { MTL_PAT_0_WB | MTL_3_COH_2W, XE_GEM_COH_AT_LEAST_1WAY },
> };
>
> static const u32 xelp_pte_pat_table[XE_CACHE_LAST] = {
> @@ -78,27 +80,35 @@ static const u32 xelpg_pte_pat_table[XE_CACHE_LAST] = {
> [XE_CACHE_WB_1_WAY] = XELPG_PAT_WB_CACHE_1_WAY,
> };
>
> +u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
> +{
> + WARN_ON(pat_index >= xe->info.pat.n_entries);
> + return xe->info.pat.table[pat_index].coh_mode;
> +}
> +
> unsigned int xe_pat_get_index(struct xe_device *xe, enum xe_cache_level cache)
> {
> WARN_ON(cache >= XE_CACHE_LAST);
> return (xe->pat_table).pte_pat_table[cache];
> }
>
> -static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
> +static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[],
> + int n_entries)
> {
> for (int i = 0; i < n_entries; i++) {
> struct xe_reg reg = XE_REG(_PAT_INDEX(i));
>
> - xe_mmio_write32(gt, reg, table[i]);
> + xe_mmio_write32(gt, reg, table[i].value);
> }
> }
>
> -static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
> +static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
> + int n_entries)
> {
> for (int i = 0; i < n_entries; i++) {
> struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));
>
> - xe_gt_mcr_multicast_write(gt, reg_mcr, table[i]);
> + xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value);
> }
> }
>
> @@ -111,6 +121,7 @@ int xe_pat_init_early(struct xe_device *xe)
> xe->info.pat.table = pvc_pat_table;
> xe->info.pat.n_entries = ARRAY_SIZE(pvc_pat_table);
> } else if (GRAPHICS_VERx100(xe) <= 1210) {
> + WARN_ON_ONCE(!IS_DGFX(xe) && !xe->info.has_llc);
> xe->info.pat.table = tgl_pat_table;
> xe->info.pat.n_entries = ARRAY_SIZE(tgl_pat_table);
> } else {
> diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
> index 2f89503233b9..809332ff08d5 100644
> --- a/drivers/gpu/drm/xe/xe_pat.h
> +++ b/drivers/gpu/drm/xe/xe_pat.h
> @@ -28,9 +28,27 @@
> struct xe_gt;
> struct xe_device;
>
> +/**
> + * struct xe_pat_table_entry - The pat_index encoding and other meta information.
> + */
> +struct xe_pat_table_entry {
> + /**
> + * @value: The platform specific value encoding the various memory
> + * attributes (this maps to some fixed pat_index). So things like
> + * caching, coherency, compression etc can be encoded here.
> + */
> + u32 value;
We probably want a blank line here to keep things readable. Otherwise,
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> + /**
> + * @coh_mode: The GPU coherency mode that @value maps to. Either
> + * XE_GEM_COH_NONE or XE_GEM_COH_AT_LEAST_1WAY.
> + */
> + u16 coh_mode;
> +};
> +
> int xe_pat_init_early(struct xe_device *xe);
> void xe_pat_init(struct xe_gt *gt);
> void xe_pte_pat_init(struct xe_device *xe);
> unsigned int xe_pat_get_index(struct xe_device *xe, enum xe_cache_level cache);
> +u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);
>
> #endif
> --
> 2.41.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
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