[Intel-xe] [PATCH] drm/xe/regs: Add definition for the PERF_LIMIT_REASONS register

[Lucas De Marchi]

On Mon, Sep 18, 2023 at 12:47:57PM +0530, Sujaritha Sundaresan wrote:
>Adding the definitions for the perf limit reasons register. This will
>be extensively used in frequency testing as well as the definition of
>several sysfs attributes.
>
>Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan at intel.com>

we don't add registers in separate patches. Please add the register when
it's used, only defining the bitfields that you care about.

Lucas De Marchi

>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index e13fbbdf6929..f9ba57c3bc4b 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -410,4 +410,17 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)
>
>+#define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
>+#define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
>+#define   PROCHOT_MASK				REG_BIT(0)
>+#define   THERMAL_LIMIT_MASK			REG_BIT(1)
>+#define   RATL_MASK				REG_BIT(5)
>+#define   VR_THERMALERT_MASK			REG_BIT(6)
>+#define   VR_TDC_MASK				REG_BIT(7)
>+#define   POWER_LIMIT_4_MASK			REG_BIT(8)
>+#define   POWER_LIMIT_1_MASK			REG_BIT(10)
>+#define   POWER_LIMIT_2_MASK			REG_BIT(11)
>+#define   GT0_PERF_LIMIT_REASONS_LOG_MASK	REG_GENMASK(31, 16)
>+#define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)
>+
> #endif
>-- 
>2.25.1
>