[Intel-xe] ✓ CI.checkpatch: success for drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

[Patchwork]

== Series Details ==

Series: drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset
URL   : https://patchwork.freedesktop.org/series/123920/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 87ffce994c4dc049274056a33911e142071a40c4
Author: Gustavo Sousa <gustavo.sousa at intel.com>
Date:   Tue Sep 19 11:41:10 2023 -0300

    drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset
    
    Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C
    behavior. If we do not properly reset them, we would miss delivery of
    interrupts if a pending bit is set when enabling IRQs.
    
    As an example, the display part of our probe routine contains paths
    where we wait for vblank interrupts. If a display interrupt was already
    pending when enabling IRQs, we would time out waiting for the vblank.
    
    That in fact happened recently when modprobing Xe on a Lunar Lake with a
    specific configuration; and that's how we found out we were missing this
    step in the IRQ enabling logic.
    
    Fix the issue by clearing GFX_MSTR_IRQ as part of the IRQ reset.
    
    BSpec: 50875, 54028, 62357
    Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
+ /mt/dim checkpatch fac2e20c785bd790c250e4f4799dfa28e44e7082 drm-intel
87ffce994 drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset