[Intel-xe] [PATCH 1/2] drm/xe: Avoid overflow on shift left

[Lucas De Marchi]

The current logic only works with the value read from the register being
up to 16 bits. We should also not be using bits other than
XELP_EU_ENABLE_MASK to define the EU fuses.

Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
---
 drivers/gpu/drm/xe/xe_gt_topology.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index a8d7f272c30a..011ad7f2325c 100644
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -36,7 +36,7 @@ static void
 load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
 {
 	struct xe_device *xe = gt_to_xe(gt);
-	u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE);
+	u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE) & XELP_EU_MASK;
 	u32 val = 0;
 	int i;
 
-- 
2.40.1