[Intel-xe] [PATCH 1/3] drm/xe/display: Add writing of remapped dpt
Juha-Pekka Heikkila
juhapekka.heikkila at gmail.com
Fri Sep 22 11:17:19 UTC 2023
Xe need to use remapped display page table for tiled framebuffers
on anywhere else than DG2. Here add function to write such dpt
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 3422942a9951..b7b587c41690 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -40,6 +40,31 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
*dpt_ofs = ALIGN(*dpt_ofs, 4096);
}
+static void
+write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
+ u32 bo_ofs, u32 width, u32 height, u32 src_stride,
+ u32 dst_stride)
+{
+ u32 column, row;
+
+ for (row = 0; row < height; row++) {
+ u32 src_idx = src_stride * row + bo_ofs;
+
+ for (column = 0; column < width; column++) {
+ iosys_map_wr(map, *dpt_ofs, u64,
+ xe_ggtt_pte_encode(bo, src_idx * XE_PAGE_SIZE));
+ *dpt_ofs += 8;
+ src_idx ++;
+ }
+
+ /* The DE ignores the PTEs for the padding tiles */
+ *dpt_ofs += (dst_stride - width) * 8;
+ }
+
+ /* Align to next page */
+ *dpt_ofs = ALIGN(*dpt_ofs, 4096);
+}
+
static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
const struct i915_gtt_view *view,
struct i915_vma *vma)
--
2.25.1
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