[Intel-xe] ✓ CI.checkpatch: success for drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset (rev4)

[Patchwork]

== Series Details ==

Series: drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset (rev4)
URL   : https://patchwork.freedesktop.org/series/123920/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit c377401876b74a96b084342d21752e5566f34c04
Author: Gustavo Sousa <gustavo.sousa at intel.com>
Date:   Tue Sep 26 19:19:15 2023 -0300

    drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset
    
    Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C
    behavior. If we do not properly reset them, we would miss delivery of
    interrupts if a pending bit is set when enabling IRQs.
    
    As an example, the display part of our probe routine contains paths
    where we wait for vblank interrupts. If a display interrupt was already
    pending when enabling IRQs, we would time out waiting for the vblank.
    
    That in fact happened recently when modprobing Xe on a Lunar Lake with a
    specific configuration; and that's how we found out we were missing this
    step in the IRQ enabling logic.
    
    Fix the issue by clearing GFX_MSTR_IRQ as part of the IRQ reset.
    
    v2:
      - Make resetting GFX_MSTR_IRQ be the last step to avoid bit
        re-latching. (Ville)
    v3:
      - Swap nesting order: guard loop with the IP version check instead of
        doing the check at each iteration. (Lucas)
    v4:
      - Add braces for the "if" statement guarding the loop to make the
        compiler happy. (Gustavo)
    
    BSpec: 50875, 54028, 62357
    Cc: Matt Roper <matthew.d.roper at intel.com>
    Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
    Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
    Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
+ /mt/dim checkpatch fc8ec3c56efa5c15b630ddc17c89100440fe03ef drm-intel
c37740187 drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset