[Intel-xe] [PATCH v2 08/11] drm/xe/pat: Keep track of relevant indexes

[Matt Roper]

On Tue, Sep 26, 2023 at 03:36:28PM -0700, Lucas De Marchi wrote:
> Some of the PAT entries are relevant for own driver use, which varies

"our own?"  Or maybe even "internal?"

> per platform. Let the PAT early initialization set what they should
> point to so the rest of the driver can use them where needed.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

With a fix to the first sentence above.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_device_types.h |  2 ++
>  drivers/gpu/drm/xe/xe_pat.c          | 12 ++++++++++++
>  drivers/gpu/drm/xe/xe_pt_types.h     |  1 +
>  3 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 98835ee058f5..7d0f2109c23a 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -15,6 +15,7 @@
>  #include "xe_devcoredump_types.h"
>  #include "xe_gt_types.h"
>  #include "xe_platform_types.h"
> +#include "xe_pt_types.h"
>  #include "xe_pmu.h"
>  #include "xe_step_types.h"
>  
> @@ -342,6 +343,7 @@ struct xe_device {
>  		const u32 *table;
>  		/** Number of PAT entries */
>  		int n_entries;
> +		u32 idx[__XE_CACHE_LEVEL_COUNT];
>  	} pat;
>  
>  	/** @d3cold: Encapsulate d3cold related stuff */
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 234d0ccd97c9..6efa44556689 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -108,10 +108,16 @@ void xe_pat_init_early(struct xe_device *xe)
>  		xe->pat.ops = &xelpg_pat_ops;
>  		xe->pat.table = xelpg_pat_table;
>  		xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 2;
> +		xe->pat.idx[XE_CACHE_WT] = 1;
> +		xe->pat.idx[XE_CACHE_WB] = 3;
>  	} else if (xe->info.platform == XE_PVC) {
>  		xe->pat.ops = &xehp_pat_ops;
>  		xe->pat.table = xehpc_pat_table;
>  		xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 0;
> +		xe->pat.idx[XE_CACHE_WT] = 2;
> +		xe->pat.idx[XE_CACHE_WB] = 3;
>  	} else if (xe->info.platform == XE_DG2) {
>  		/*
>  		 * Programming like XeHP, but same table as previous platforms
> @@ -119,10 +125,16 @@ void xe_pat_init_early(struct xe_device *xe)
>  		xe->pat.ops = &xehp_pat_ops;
>  		xe->pat.table = xelp_pat_table;
>  		xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 2;
> +		xe->pat.idx[XE_CACHE_WB] = 0;
>  	} else if (GRAPHICS_VERx100(xe) <= 1210) {
>  		xe->pat.ops = &xelp_pat_ops;
>  		xe->pat.table = xelp_pat_table;
>  		xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);
> +		xe->pat.idx[XE_CACHE_NONE] = 3;
> +		xe->pat.idx[XE_CACHE_WT] = 2;
> +		xe->pat.idx[XE_CACHE_WB] = 0;
>  	} else {
>  		/*
>  		 * Going forward we expect to need new PAT settings for most
> diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
> index 64e3921a0f46..bf5000499251 100644
> --- a/drivers/gpu/drm/xe/xe_pt_types.h
> +++ b/drivers/gpu/drm/xe/xe_pt_types.h
> @@ -17,6 +17,7 @@ enum xe_cache_level {
>  	XE_CACHE_NONE,
>  	XE_CACHE_WT,
>  	XE_CACHE_WB,
> +	__XE_CACHE_LEVEL_COUNT,
>  };
>  
>  #define XE_VM_MAX_LEVEL 4
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation