[Intel-xe] [RFC PATCH 0/3] Xe dma fence handling on atomic commit

[Jouni Högander]

This patch set is reverting current changes to fence handling during
atomic commit. A new compatibility header addressing lack of
i915_sw_fence implementation in Xe is introduced. This header contains
dma fence handling during atomic commit for Xe driver and interfaces
are following current i915_sw_fence implementation.

Additionally change to current atomic commit code and i915_sw_fence is
needed. This patch has to go to i915 upstream. It is needed due to
missing GT reset status in Xe driver. In case of i915 this status is
polled while waiting for dma fences and in case of GT reset atomic
commit is completed even if dma fences are not signalled. I'm not sure
how GT reset is supposed to be handled in case of Xe? Maybe dma fences
are signaled if GT reset occures?

Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Jani Nikula <jani.nikula at intel.com>

Jouni Högander (3):
  Revert "FIXME: drm/i915: fence stuff"
  drm/i915/display: Move fence completion wait away from display code
  fixup! drm/xe/display: Implement display support

 drivers/gpu/drm/i915/display/intel_atomic.c   |   2 -
 drivers/gpu/drm/i915/display/intel_display.c  |  50 +-------
 .../drm/i915/display/intel_display_types.h    |   3 +-
 drivers/gpu/drm/i915/i915_sw_fence.c          |  28 +++++
 drivers/gpu/drm/i915/i915_sw_fence.h          |   4 +
 .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 -
 .../xe/compat-i915-headers/i915_sw_fence.h    | 111 ++++++++++++++++++
 7 files changed, 145 insertions(+), 54 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/i915_sw_fence.h

-- 
2.34.1