[Intel-xe] [RFC PATCH 0/3] Xe dma fence handling on atomic commit

Hogander, Jouni jouni.hogander at intel.com
Wed Sep 27 10:45:28 UTC 2023


On Wed, 2023-09-27 at 12:33 +0200, Maarten Lankhorst wrote:
> Hey,
> 
> When we wrote the original display support, we purposely decided on
> not 
> adding i915_sw_fence support.
> 
> In this case, I think a better approach would be to remove this code 
> from i915 as well, and end up with cleaner display code for both
> drivers.

Yes, I agree eventually this would be the goal. I did some experiments
here:

https://patchwork.freedesktop.org/patch/558982/?series=123898&rev=4

Which is replacing i915_sw_fence with same code I'm using for Xe driver
in this patch set. The problem is GPU reset detection. I don't have
currently good ideas how to tackle that without compromizing i915
functionality in this scenario -> ended up doing this only for Xe to
ensure this is not blocking upstreaming Xe. Would this be acceptable as
temporary solution to be solved after upstreaming? Anyways what I'm
doing in these patches is not really an i915_sw_fence revised, but
using dma_fences.

BR,

Jouni Högander


> Cheers,
> ~Maarten
> 
> On 2023-09-27 09:31, Jouni Högander wrote:
> > This patch set is reverting current changes to fence handling
> > during
> > atomic commit. A new compatibility header addressing lack of
> > i915_sw_fence implementation in Xe is introduced. This header
> > contains
> > dma fence handling during atomic commit for Xe driver and
> > interfaces
> > are following current i915_sw_fence implementation.
> > 
> > Additionally change to current atomic commit code and i915_sw_fence
> > is
> > needed. This patch has to go to i915 upstream. It is needed due to
> > missing GT reset status in Xe driver. In case of i915 this status
> > is
> > polled while waiting for dma fences and in case of GT reset atomic
> > commit is completed even if dma fences are not signalled. I'm not
> > sure
> > how GT reset is supposed to be handled in case of Xe? Maybe dma
> > fences
> > are signaled if GT reset occures?
> > 
> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Cc: Jani Nikula <jani.nikula at intel.com>
> > 
> > Jouni Högander (3):
> >    Revert "FIXME: drm/i915: fence stuff"
> >    drm/i915/display: Move fence completion wait away from display
> > code
> >    fixup! drm/xe/display: Implement display support
> > 
> >   drivers/gpu/drm/i915/display/intel_atomic.c   |   2 -
> >   drivers/gpu/drm/i915/display/intel_display.c  |  50 +-------
> >   .../drm/i915/display/intel_display_types.h    |   3 +-
> >   drivers/gpu/drm/i915/i915_sw_fence.c          |  28 +++++
> >   drivers/gpu/drm/i915/i915_sw_fence.h          |   4 +
> >   .../gpu/drm/xe/compat-i915-headers/i915_drv.h |   1 -
> >   .../xe/compat-i915-headers/i915_sw_fence.h    | 111
> > ++++++++++++++++++
> >   7 files changed, 145 insertions(+), 54 deletions(-)
> >   create mode 100644 drivers/gpu/drm/xe/compat-i915-
> > headers/i915_sw_fence.h
> > 



More information about the Intel-xe mailing list