[Intel-xe] ✓ CI.checkpatch: success for PAT and cache coherency support (rev7)

[Patchwork]

== Series Details ==

Series: PAT and cache coherency support (rev7)
URL   : https://patchwork.freedesktop.org/series/123027/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit af55f15bc9bb795bbe7a55dc6a18924ec42c6582
Author: Matthew Auld <matthew.auld at intel.com>
Date:   Thu Sep 28 11:05:43 2023 +0100

    drm/xe/uapi: support pat_index selection with vm_bind
    
    Allow userspace to directly control the pat_index for a given vm
    binding. This should allow directly controlling the coherency, caching
    and potentially other stuff in the future for the ppGTT binding.
    
    The exact meaning behind the pat_index is very platform specific (see
    BSpec or PRMs) but effectively maps to some predefined memory
    attributes. From the KMD pov we only care about the coherency that is
    provided by the pat_index, which falls into either NONE, 1WAY or 2WAY.
    The vm_bind coherency mode for the given pat_index needs to be at least
    as coherent as the coh_mode that was set at object creation. For
    platforms that lack the explicit coherency mode, we treat UC/WT/WC as
    NONE and WB as AT_LEAST_1WAY.
    
    For userptr mappings we lack a corresponding gem object, so the expected
    coherency mode is instead implicit and must fall into either 1WAY or
    2WAY. Trying to use NONE will be rejected by the kernel. For imported
    dma-buf (from a different device) the coherency mode is also implicit
    and must also be either 1WAY or 2WAY i.e AT_LEAST_1WAY.
    
    v2:
      - Undefined coh_mode(pat_index) can now be treated as programmer
        error. (Matt Roper)
      - We now allow gem_create.coh_mode <= coh_mode(pat_index), rather than
        having to match exactly. This ensures imported dma-buf can always
        just use 1way (or even 2way), now that we also bundle 1way/2way into
        at_least_1way. We still require 1way/2way for external dma-buf, but
        the policy can now be the same for self-import, if desired.
      - Use u16 for pat_index in uapi. u32 is massive overkill. (José)
      - Move as much of the pat_index validation as we can into
        vm_bind_ioctl_check_args. (José)
    v3 (Matt Roper):
      - Split the pte_encode() refactoring into separate patch.
    v4:
      - Rebase
    
    Bspec: 45101, 44235 #xe
    Bspec: 70552, 71582, 59400 #xe2
    Signed-off-by: Matthew Auld <matthew.auld at intel.com>
    Cc: Pallavi Mishra <pallavi.mishra at intel.com>
    Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
    Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
    Cc: Lucas De Marchi <lucas.demarchi at intel.com>
    Cc: Matt Roper <matthew.d.roper at intel.com>
    Cc: José Roberto de Souza <jose.souza at intel.com>
    Cc: Filip Hazubski <filip.hazubski at intel.com>
    Cc: Carl Zhang <carl.zhang at intel.com>
    Cc: Effie Yu <effie.yu at intel.com>
+ /mt/dim checkpatch 7c58b58522cf124dd324fbf95d9dd838fac36bcb drm-intel
29b350c5f drm/xe/pat: trim the xelp PAT table
535470250 drm/xe: directly use pat_index for pte_encode
c45ed0c45 drm/xe/uapi: Add support for cache and coherency mode
26fbadf40 drm/xe/pat: annotate pat_index with coherency mode
af55f15bc drm/xe/uapi: support pat_index selection with vm_bind