[Intel-xe] ✓ CI.checkpatch: success for drm/xe: Leverage ComputeCS read L3 caching

[Patchwork]

== Series Details ==

Series: drm/xe: Leverage ComputeCS read L3 caching
URL   : https://patchwork.freedesktop.org/series/124431/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 31e7ecc35e3fc86e63b215a84b17eb2fa7d5eee9
Author: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
Date:   Thu Sep 28 22:15:39 2023 -0700

    drm/xe: Leverage ComputeCS read L3 caching
    
    On platforms that support read L3 caching, set the default mocs index in
    CCS RING_CMD_CTL to levarage the read caching in L3.
    
    Currently PVC and Xe2 platforms have the support.
    
    Bspec: 72161
    Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
+ /mt/dim checkpatch 9a795b4f0ebe6bf70b1c873e323c3e0e7e113c64 drm-intel
31e7ecc35 drm/xe: Leverage ComputeCS read L3 caching