[Intel-xe] [PATCH v6 2/5] drm/xe: directly use pat_index for pte_encode

[Matthew Auld]

On 28/09/2023 14:15, Lucas De Marchi wrote:
> On Thu, Sep 28, 2023 at 11:05:40AM +0100, Matthew Auld wrote:
>> diff --git a/drivers/gpu/drm/xe/xe_pt_types.h 
>> b/drivers/gpu/drm/xe/xe_pt_types.h
>> index bd6645295fe6..355fa8f014e9 100644
>> --- a/drivers/gpu/drm/xe/xe_pt_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pt_types.h
>> @@ -38,14 +38,14 @@ struct xe_pt {
>>
>> struct xe_pt_ops {
>>     u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset,
>> -                 enum xe_cache_level cache, u32 pt_level);
>> +                 u16 pat_index, u32 pt_level);
>>     u64 (*pte_encode_vma)(u64 pte, struct xe_vma *vma,
>> -                  enum xe_cache_level cache, u32 pt_level);
>> +                  u16 pat_index, u32 pt_level);
>>     u64 (*pte_encode_addr)(struct xe_device *xe, u64 addr,
>> -                   enum xe_cache_level cache,
>> +                   u16 pat_index,
>>                    u32 pt_level, bool devmem, u64 flags);
>>     u64 (*pde_encode_bo)(struct xe_bo *bo, u64 bo_offset,
>> -                 const enum xe_cache_level cache);
>> +                 const u16 pat_index);
> 
> I think the const enum was a copy-past mistake on my side. Might as well
> just remove it here?
> 
> Other question is: why is pat_index a u16 instead of u8? I don't think
> we have any plans to support more than 256, do we?

It's likely overkill. I was just worried since we are already at ~32 on 
xe2 and every time you add a new bit/memory attribute you might get a 
combinatorial explosion.

I can make it u8 if you prefer.

> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> 
> Lucas De Marchi