[Intel-xe] [PATCH 4/7] drm/xe/xe2: Add one more bit to encode PAT to ppgtt entries

[Mishra, Pallavi]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Lucas
> De Marchi
> Sent: Thursday, September 28, 2023 10:03 PM
> To: intel-xe at lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi at intel.com>
> Subject: [Intel-xe] [PATCH 4/7] drm/xe/xe2: Add one more bit to encode PAT
> to ppgtt entries
> 
> Xe2 adds one more bit to cover all the possible 32 entries. Although those
> entries are not used by internal kernel code paths, it's expected that userspace
> will make use of it.
> 
> Bspec: 59510
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_bo.h | 1 +
>  drivers/gpu/drm/xe/xe_vm.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h index
> 5090bdd1e462..7ffc26446d2e 100644
> --- a/drivers/gpu/drm/xe/xe_bo.h
> +++ b/drivers/gpu/drm/xe/xe_bo.h
> @@ -40,6 +40,7 @@
>  #define XE_BO_INTERNAL_64K		BIT(31)
> 
>  #define XELPG_PPGTT_PTE_PAT3		BIT_ULL(62)
> +#define XE2_PPGTT_PTE_PAT4		BIT_ULL(61)
>  #define XE_PPGTT_PTE_PAT2		BIT_ULL(7)
>  #define XE_PPGTT_PTE_PAT1		BIT_ULL(4)
>  #define XE_PPGTT_PTE_PAT0		BIT_ULL(3)
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index
> 140a70d91d76..7e5f4bbea451 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -1223,6 +1223,9 @@ static u64 pte_encode_cache(struct xe_device *xe,
> enum xe_cache_level cache)
>  	if (pat_index & BIT(3))
>  		pte |= XELPG_PPGTT_PTE_PAT3;
> 
> +	if (pat_index & (BIT(4)))
> +		pte |= XE2_PPGTT_PTE_PAT4;
> +
>  	return pte;
>  }
> 
Reviewed-by: Pallavi Mishra <pallavi.mishra at intel.com>

> --
> 2.40.1