[Intel-xe] [PATCH 3/7] drm/xe/xe2: Follow XeHPC for TLB invalidation

[Matt Roper]

On Thu, Sep 28, 2023 at 10:02:49PM -0700, Lucas De Marchi wrote:
> Register GUC_TLB_INV_CR is gone in xe2. When GuC submission is not yet
> enabled, make sure to follow the same path as XeHPC.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Matches the invalidation descriptor structure from bspec 59311.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

Although I am uncertain that the general invalidation code here is
entirely correct, even for PVC.  Since completion only gets delivered to
the GuC (which isn't up and running yet at the point we're using this),
we should probably be checking that the 'valid' bit has returned to 0
from the previous request before trying to submit another invalidation
request.  But assuming that's needed, it would be a change for a
different patch.


Matt

> ---
>  drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 99b54794917e..d7b3d008ce57 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -263,7 +263,7 @@ static void ggtt_invalidate_gt_tlb(struct xe_gt *gt)
>  	} else if (xe_device_uc_enabled(gt_to_xe(gt))) {
>  		struct xe_device *xe = gt_to_xe(gt);
>  
> -		if (xe->info.platform == XE_PVC) {
> +		if (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20) {
>  			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC1,
>  					PVC_GUC_TLB_INV_DESC1_INVALIDATE);
>  			xe_mmio_write32(gt, PVC_GUC_TLB_INV_DESC0,
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation