[PATCH v2] drm/xe/xe2: Add workaround 18033852989

[Ghimiray, Himal Prasad]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper at intel.com>
> Sent: 01 April 2024 21:42
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray at intel.com>
> Cc: intel-xe at lists.freedesktop.org; De Marchi, Lucas
> <lucas.demarchi at intel.com>
> Subject: Re: [PATCH v2] drm/xe/xe2: Add workaround 18033852989
> 
> On Mon, Apr 01, 2024 at 09:49:07PM +0530, Himal Prasad Ghimiray wrote:
> > This workaround applies to RCS engine's context, hence added as LRC
> > workaround.
> >
> > v2
> 
> I didn't notice that there was a v2 when I sent my feedback on v1, but just to
> note it here, COMMON_SLICE_CHICKEN1 is a masked register and our definition
> below seems to be missing the XE_REG_OPTION_MASKED flag.
> 
> In the past that didn't matter since the register definition was only used to
> whitelist this register for userspace access, but now that we're actually changing
> the register contents we'll need to add the flag, otherwise the bit updates won't
> take effect.
Thanks Matt. Missed this detail from BSPEC. Will modify and resend patch.
> 
> 
> Matt
> 
> > - Fix commit description as lrc workaround instead of engine.(Lucas)
> >
> > Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> > Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> > ---
> >  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
> >  drivers/gpu/drm/xe/xe_wa.c           | 4 ++++
> >  2 files changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > index d5b21f03beaa..9728d9da9931 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > @@ -98,6 +98,7 @@
> >  #define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)
> >
> >  #define COMMON_SLICE_CHICKEN1			XE_REG(0x7010)
> > +#define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)
> >
> >  #define HIZ_CHICKEN					XE_REG(0x7018,
> XE_REG_OPTION_MASKED)
> >  #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE
> 	REG_BIT(14)
> > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> > index 74b33a3845f2..c904e55ced9c 100644
> > --- a/drivers/gpu/drm/xe/xe_wa.c
> > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > @@ -579,6 +579,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
> >  		       ENGINE_CLASS(RENDER)),
> >  	  XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE),
> ENABLE_SEMAPHORE_POLL_BIT))
> >  	},
> > +	{ XE_RTP_NAME("18033852989"),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
> > +	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN1,
> DISABLE_BOTTOM_CLIP_RECTANGLE_TEST))
> > +	},
> >
> >  	{}
> >  };
> > --
> > 2.25.1
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation