[PATCH 11/11] drm/xe/xe2hpm: Add initial set of workarounds

[Matt Roper]

On Tue, Apr 02, 2024 at 06:17:24PM +0530, Balasubramani Vivekanandan wrote:
> From: Gustavo Sousa <gustavo.sousa at intel.com>
> 
> Define the initial set of workarounds for Xe2_HPM.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  4 ++++
>  drivers/gpu/drm/xe/xe_wa.c           | 32 ++++++++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 17cc9b6c9536..126baed6a99f 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -279,6 +279,10 @@
>  #define FORCEWAKE_GT				XE_REG(0xa188)
>  
>  #define PG_ENABLE				XE_REG(0xa210)
> +#define   VD2_MFXVDENC_POWERGATE_ENABLE		REG_BIT(8)
> +#define   VD2_HCP_POWERGATE_ENABLE		REG_BIT(7)
> +#define   VD0_MFXVDENC_POWERGATE_ENABLE		REG_BIT(4)
> +#define   VD0_HCP_POWERGATE_ENABLE		REG_BIT(3)
>  
>  #define CTC_MODE				XE_REG(0xa26c)
>  #define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index a163a764d25e..824481cd2247 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -228,6 +228,28 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
>  
> +	/* Xe2_HPM */
> +
> +	{ XE_RTP_NAME("16021867713"),
> +	  XE_RTP_RULES(MEDIA_VERSION(1301),
> +		       ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
> +	{ XE_RTP_NAME("14020316580"),
> +	  XE_RTP_RULES(MEDIA_VERSION(1301)),
> +	  XE_RTP_ACTIONS(CLR(PG_ENABLE,
> +			     VD0_HCP_POWERGATE_ENABLE |
> +			     VD0_MFXVDENC_POWERGATE_ENABLE |
> +			     VD2_HCP_POWERGATE_ENABLE |
> +			     VD2_MFXVDENC_POWERGATE_ENABLE)),
> +	},
> +	{ XE_RTP_NAME("14019449301"),
> +	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
> +
>  	{}
>  };
>  
> @@ -508,6 +530,16 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
>  	},
>  
> +	/* Xe2_HPM */
> +
> +	{ XE_RTP_NAME("16021639441"),
> +	  XE_RTP_RULES(MEDIA_VERSION(1301)),
> +	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
> +			     GHWSP_CSB_REPORT_DIS |
> +			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
> +			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> +	},
> +
>  	{}
>  };
>  
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation