✓ CI.Patch_applied: success for Enable dislay support for Battlemage (rev2)

[Patchwork]

== Series Details ==

Series: Enable dislay support for Battlemage (rev2)
URL   : https://patchwork.freedesktop.org/series/131983/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 23e6199ddb93 drm-tip: 2024y-04m-03d-07h-14m-06s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/display: Prepare to handle new C20 PLL register address
Applying: drm/xe/bmg: Add BMG platform definition
Applying: drm/xe/bmg: Define IS_BATTLEMAGE macro
Applying: drm/i915/bmg: Define IS_BATTLEMAGE macro
Applying: drm/i915/xe2: Skip CCS modifiers for Xe2 platforms
Applying: drm/i915/xe2hpd: Initial cdclk table
Applying: Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
Applying: drm/i915/bmg: Extend DG2 tc check to future
Applying: drm/i915/xe2hpd: Properly disable power in port A
Applying: drm/i915/xe2hpd: Add new C20 PLL register address
Applying: drm/i915/xe2hpd: Add support for eDP PLL configuration
Applying: drm/i915/xe2hpd: update pll values in sync with Bspec
Applying: drm/i915/xe2hpd: Add display info
Applying: drm/i915/xe2hpd: Add missing chicken bit register programming
Applying: drm/xe/display: Lane reversal requires writes to both context lanes
Applying: drm/xe/xe2hpd: Define a new DRAM type INTEL_DRAM_GDDR
Applying: drm/i915/xe2hpd: Add max memory bandwidth algorithm
Applying: drm/i915/display: Enable RM timeout detection
Applying: drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
Applying: drm/i915/bmg: BMG should re-use MTL's south display logic
Applying: drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
Applying: drm/xe/gt_print: add xe_gt_err_once()
Applying: drm/xe/device: implement transient flush
Applying: drm/i915/display: perform transient flush
Applying: drm/xe/bmg: Enable the display support