[PATCH 1/2] drm/xe/tile: Set default memory placement for BOs

[Lucas De Marchi]

On Wed, Apr 03, 2024 at 05:47:58PM +0200, Nirmoy Das wrote:
>>diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
>>index bae042b35fa8..8781ee15c253 100644
>>--- a/drivers/gpu/drm/xe/xe_bo.h
>>+++ b/drivers/gpu/drm/xe/xe_bo.h
>>@@ -23,17 +23,16 @@
>>  #define XE_DEFAULT_GTT_SIZE_MB          3072ULL /* 3GB by default */
>>-#define XE_BO_FLAG_USER		BIT(0)
>>+#define XE_BO_FLAG_USER			BIT(0)
>>  /* The bits below need to be contiguous, or things break */
>>  #define XE_BO_FLAG_SYSTEM		BIT(1)
>>  #define XE_BO_FLAG_VRAM0		BIT(2)
>>  #define XE_BO_FLAG_VRAM1		BIT(3)
>>-#define XE_BO_FLAG_VRAM_MASK		(XE_BO_FLAG_VRAM0 | XE_BO_FLAG_VRAM1)
>>-/* -- */
>>  #define XE_BO_FLAG_STOLEN		BIT(4)
>>-#define XE_BO_FLAG_VRAM_IF_DGFX(tile)	(IS_DGFX(tile_to_xe(tile)) ? \
>>-					 XE_BO_FLAG_VRAM0 << (tile)->id : \
>>-					 XE_BO_FLAG_SYSTEM)
>
>This should happen in the following patch.  Otherwise this looks good 
>to me.

oops, yeah. Bad squash on my side.

>
>Reviewed-by: Nirmoy Das <nirmoy.das at intel.com>

thanks
Lucas De Marchi