[PATCH 3/5] drm/xe/guc: Add PF2GUC_UPDATE_VGT_POLICY to ABI
Piotr Piórkowski
piotr.piorkowski at intel.com
Wed Apr 10 16:02:15 UTC 2024
Michal Wajdeczko <michal.wajdeczko at intel.com> wrote on śro [2024-kwi-10 14:31:23 +0200]:
> In upcoming patches the PF driver will add support to change GuC
> policies and will need to use PF2GUC_UPDATE_VGT_POLICY messages.
> Add necessary definitions to our GuC firmware ABI header.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
> .../gpu/drm/xe/abi/guc_actions_sriov_abi.h | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/abi/guc_actions_sriov_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_sriov_abi.h
> index 12ee5e9e831f..5051e3b866df 100644
> --- a/drivers/gpu/drm/xe/abi/guc_actions_sriov_abi.h
> +++ b/drivers/gpu/drm/xe/abi/guc_actions_sriov_abi.h
> @@ -213,6 +213,53 @@
> #define GUC_PF_NOTIFY_VF_PAUSE_DONE 3u
> #define GUC_PF_NOTIFY_VF_FIXUP_DONE 4u
>
> +/**
> + * DOC: PF2GUC_UPDATE_VGT_POLICY
> + *
> + * This message is optionaly used by the PF to set `GuC VGT Policy KLVs`_.
typo
> + *
> + * This message must be sent as `CTB HXG Message`_.
> + *
> + * +---+-------+--------------------------------------------------------------+
> + * | | Bits | Description |
> + * +===+=======+==============================================================+
> + * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_HOST_ |
> + * | +-------+--------------------------------------------------------------+
> + * | | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_ |
> + * | +-------+--------------------------------------------------------------+
> + * | | 27:16 | MBZ |
> + * | +-------+--------------------------------------------------------------+
> + * | | 15:0 | ACTION = _`GUC_ACTION_PF2GUC_UPDATE_VGT_POLICY` = 0x5502 |
> + * +---+-------+--------------------------------------------------------------+
> + * | 1 | 31:0 | **CFG_ADDR_LO** - dword aligned GGTT offset that |
> + * | | | represents the start of `GuC VGT Policy KLVs`_ list. |
> + * +---+-------+--------------------------------------------------------------+
> + * | 2 | 31:0 | **CFG_ADDR_HI** - upper 32 bits of above offset. |
> + * +---+-------+--------------------------------------------------------------+
> + * | 3 | 31:0 | **CFG_SIZE** - size (in dwords) of the config buffer |
> + * +---+-------+--------------------------------------------------------------+
> + *
> + * +---+-------+--------------------------------------------------------------+
> + * | | Bits | Description |
> + * +===+=======+==============================================================+
> + * | 0 | 31 | ORIGIN = GUC_HXG_ORIGIN_GUC_ |
> + * | +-------+--------------------------------------------------------------+
> + * | | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_ |
> + * | +-------+--------------------------------------------------------------+
> + * | | 27:0 | **COUNT** - number of KLVs successfully applied |
> + * +---+-------+--------------------------------------------------------------+
> + */
> +#define GUC_ACTION_PF2GUC_UPDATE_VGT_POLICY 0x5502u
> +
> +#define PF2GUC_UPDATE_VGT_POLICY_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
> +#define PF2GUC_UPDATE_VGT_POLICY_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
> +#define PF2GUC_UPDATE_VGT_POLICY_REQUEST_MSG_1_CFG_ADDR_LO GUC_HXG_REQUEST_MSG_n_DATAn
> +#define PF2GUC_UPDATE_VGT_POLICY_REQUEST_MSG_2_CFG_ADDR_HI GUC_HXG_REQUEST_MSG_n_DATAn
> +#define PF2GUC_UPDATE_VGT_POLICY_REQUEST_MSG_3_CFG_SIZE GUC_HXG_REQUEST_MSG_n_DATAn
> +
> +#define PF2GUC_UPDATE_VGT_POLICY_RESPONSE_MSG_LEN GUC_HXG_RESPONSE_MSG_MIN_LEN
> +#define PF2GUC_UPDATE_VGT_POLICY_RESPONSE_MSG_0_COUNT GUC_HXG_RESPONSE_MSG_0_DATA0
> +
> /**
> * DOC: PF2GUC_VF_CONTROL
> *
one typo, the rest of the code looks ok:
Reviewed-by: Piotr Piórkowski <piotr.piorkowski at intel.com>
> --
> 2.43.0
>
--
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