[PATCH v6 1/4] drm/xe/lrc: Add xe lrc ring tail function definitions
Jonathan Cavitt
jonathan.cavitt at intel.com
Mon Apr 15 21:50:09 UTC 2024
Add defintions for the functions xe_lrc_set_ring_tail and
xe_lrc_ring_tail to match the definitions for xe_lrc_set_ring_head and
xe_lrc_ring_head, respectively, except tarting the lrc tail.
These new declarations can be put to immediate use in various places,
such as when initializing the lrc, creating snapshots, and submitting
exec queues.
Signed-off-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
CC: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
CC: Brian Welty <brian.welty at intel.com>
CC: Matt Roper <matthew.d.roper at intel.com>
---
v2: Use new functions in various places.
drivers/gpu/drm/xe/xe_execlist.c | 2 +-
drivers/gpu/drm/xe/xe_guc_submit.c | 2 +-
drivers/gpu/drm/xe/xe_lrc.c | 18 ++++++++++++++----
drivers/gpu/drm/xe/xe_lrc.h | 2 ++
4 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index dece2785933c0..e46519ad683c6 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -62,7 +62,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
xe_mmio_write32(hwe->gt, RCU_MODE,
_MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
- xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
+ xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
lrc->ring.old_tail = lrc->ring.tail;
/*
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index c7d38469fb469..ecd1085619b30 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -658,7 +658,7 @@ static void submit_exec_queue(struct xe_exec_queue *q)
if (xe_exec_queue_is_parallel(q))
wq_item_append(q);
else
- xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
+ xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q))
return;
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 615bbc372ac62..7b8997cff74eb 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -787,8 +787,8 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
}
xe_lrc_write_ctx_reg(lrc, CTX_RING_START, __xe_lrc_ring_ggtt_addr(lrc));
- xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0);
- xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
+ xe_lrc_set_ring_head(lrc, 0);
+ xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
xe_lrc_write_ctx_reg(lrc, CTX_RING_CTL,
RING_CTL_SIZE(lrc->ring.size) | RING_VALID);
if (xe->info.has_asid && vm)
@@ -834,6 +834,16 @@ void xe_lrc_finish(struct xe_lrc *lrc)
xe_bo_put(lrc->bo);
}
+void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail)
+{
+ xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, tail);
+}
+
+u32 xe_lrc_ring_tail(struct xe_lrc *lrc)
+{
+ return xe_lrc_read_ctx_reg(lrc, CTX_RING_TAIL) & TAIL_ADDR;
+}
+
void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head)
{
xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, head);
@@ -847,7 +857,7 @@ u32 xe_lrc_ring_head(struct xe_lrc *lrc)
u32 xe_lrc_ring_space(struct xe_lrc *lrc)
{
const u32 head = xe_lrc_ring_head(lrc);
- const u32 tail = lrc->ring.tail;
+ const u32 tail = xe_lrc_ring_tail(lrc);
const u32 size = lrc->ring.size;
return ((head - tail - 1) & (size - 1)) + 1;
@@ -1357,7 +1367,7 @@ struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc)
snapshot->context_desc = lower_32_bits(xe_lrc_ggtt_addr(lrc));
snapshot->head = xe_lrc_ring_head(lrc);
snapshot->tail.internal = lrc->ring.tail;
- snapshot->tail.memory = xe_lrc_read_ctx_reg(lrc, CTX_RING_TAIL);
+ snapshot->tail.memory = xe_lrc_ring_tail(lrc);
snapshot->start_seqno = xe_lrc_start_seqno(lrc);
snapshot->seqno = xe_lrc_seqno(lrc);
snapshot->lrc_bo = xe_bo_get(lrc->bo);
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index d32fa31faa2cf..f355b0eeb5658 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -24,6 +24,8 @@ void xe_lrc_finish(struct xe_lrc *lrc);
size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class);
u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc);
+void xe_lrc_set_ring_tail(struct xe_lrc *lrc, u32 tail);
+u32 xe_lrc_ring_tail(struct xe_lrc *lrc);
void xe_lrc_set_ring_head(struct xe_lrc *lrc, u32 head);
u32 xe_lrc_ring_head(struct xe_lrc *lrc);
u32 xe_lrc_ring_space(struct xe_lrc *lrc);
--
2.25.1
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