[PATCH v2] drm/xe/lnl: Apply GuC Wa_13011645652

[Belgaumkar, Vinay]

On 4/16/2024 5:51 PM, John Harrison wrote:
> On 4/16/2024 12:41, Vinay Belgaumkar wrote:
>> Enable WA for a bug that could cause the C6 state machine to hang
>> during RC6 exit.
>>
>> v2: Add comment clarifying the WA (John H)
>>
>> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
>> ---
>>   drivers/gpu/drm/xe/abi/guc_klvs_abi.h |  1 +
>>   drivers/gpu/drm/xe/xe_guc_ads.c       | 34 +++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_wa_oob.rules    |  1 +
>>   3 files changed, 36 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h 
>> b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
>> index 0972113f6b81..511cf974d585 100644
>> --- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
>> +++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
>> @@ -326,6 +326,7 @@ enum xe_guc_klv_ids {
>> GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED = 0x9002,
>> GUC_WORKAROUND_KLV_ID_GAM_PFQ_SHADOW_TAIL_POLLING = 0x9005,
>> GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE = 0x9007,
>> + GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE = 0x9008,
>>   };
>>     #endif
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c 
>> b/drivers/gpu/drm/xe/xe_guc_ads.c
>> index 678ece366056..4e6fc69a4710 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
>> @@ -282,6 +282,33 @@ static size_t calculate_golden_lrc_size(struct 
>> xe_guc_ads *ads)
>>       return total_size;
>>   }
>>   +static void guc_waklv_enable_one_word(struct xe_guc_ads *ads,
>> +                      enum xe_guc_klv_ids klv_id,
>> +                      u32 value,
>> +                      u32 *offset, u32 *remain)
>> +{
>> +    u32 size;
>> +    u32 klv_entry[] = {
>> +        /* 16:16 key/length */
>> +        FIELD_PREP(GUC_KLV_0_KEY, klv_id) |
>> +        FIELD_PREP(GUC_KLV_0_LEN, 1),
>> +        value,
>> +        /* 1 dword data */
>> +    };
>> +
>> +    size = sizeof(klv_entry);
>> +
>> +    if (*remain < size) {
>> +        drm_warn(&ads_to_xe(ads)->drm,
>> +             "w/a klv buffer too small to add klv id %d\n", klv_id);
>> +    } else {
>> +        xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), *offset,
>> +                 klv_entry, size);
>> +        *offset += size;
>> +        *remain -= size;
>> +    }
>> +}
>> +
>>   static void guc_waklv_enable_simple(struct xe_guc_ads *ads,
>>                       enum xe_guc_klv_ids klv_id, u32 *offset, u32 
>> *remain)
>>   {
>> @@ -327,6 +354,13 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
>> GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE,
>>                       &offset, &remain);
>>   +    /* GuC will restore register 0xB04 to the default HW value of 
>> 0xC40 */
> This reads to me like 0xC40 is hard coded in the GuC. I would prefer 
> something like "On RC6 exit, GuC will write register 0xB04 with the 
> value provided. The default value for 0xB04 in bspec is 0xC40, so use 
> that."
Ok.
>
> John.
>
>> +    if (XE_WA(gt, 13011645652))
>> +        guc_waklv_enable_one_word(ads,
>> + GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE,
>> +                      0xC40,
>> +                      &offset, &remain);
>> +
>>       size = guc_ads_waklv_size(ads) - remain;
>>       if (!size)
>>           return;
>> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules 
>> b/drivers/gpu/drm/xe/xe_wa_oob.rules
>> index eb647d5a1e16..12fe88796a49 100644
>> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>> @@ -26,3 +26,4 @@
>>           MEDIA_VERSION(2000)
>>   16022287689    GRAPHICS_VERSION(2001)
>>           GRAPHICS_VERSION(2004)
>> +13011645652    GRAPHICS_VERSION(2004)
>