[PATCH v2 1/3] drm/xe/gsc: define GSCCS for LNL

Daniele Ceraolo Spurio daniele.ceraolospurio at intel.com
Wed Apr 17 21:13:53 UTC 2024



On 4/17/2024 1:00 PM, Lucas De Marchi wrote:
> On Tue, Apr 16, 2024 at 03:21:57PM GMT, Daniele Ceraolo Spurio wrote:
>> LNL has 1 GSCCS, same as MTL. Note that the GSCCS will be disabled until
>> we have a GSC FW defined, but having it in the list of engine is a
>> requirement to add such definition.
>
>
> ... which means we could have gone with it defined instead of the TODO?
> If so maybe good to adapt the patches for next platforms.  We already
> define other engines and rely on fuses to handle things correctly (even
> more after 
> https://lore.kernel.org/intel-xe/20240417152621.3357990-2-matthew.d.roper@intel.com/
> is merged. Just letting the firmware absence do the right thing would be
> the equivalent of that I think.

Agreed. There is a small potential issue with interrupts, but I've just 
sent a fix for it (together with this patch on its own so we can get it 
merged while we wait for mei).

Daniele

>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
>
>
> Lucas De Marchi
>
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_pci.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 3b30353dbc09..ad46ed6a2de7 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -209,7 +209,8 @@ static const struct xe_media_desc media_xelpmp = {
>> static const struct xe_media_desc media_xe2 = {
>>     .name = "Xe2_LPM / Xe2_HPM",
>>     .hw_engine_mask =
>> -        BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0), /* TODO: 
>> GSC0 */
>> +        BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0) |
>> +        BIT(XE_HW_ENGINE_GSCCS0)
>> };
>>
>> static const struct xe_device_desc tgl_desc = {
>> -- 
>> 2.43.0
>>



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