[PATCH 1/2] drm/xe/gsc: Turn off GSCCS interrupts when disabling the engine

[Lucas De Marchi]

On Wed, Apr 17, 2024 at 02:12:23PM GMT, Daniele Ceraolo Spurio wrote:
>Starting on LNL, there is a new GSCCS interrupt that is triggered when
>the GSC engine reset fails. If the HW is in a bad state, this interrupt
>might end up being triggered even if we're not using the engine, which
>will lead to a warning because we'll see it as unexpected. Since there
>is no point in handling the interrupt in this scenario, we can just
>make sure the interrupts are off when we disable the engine.
>
>Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>Cc: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/xe/xe_hw_engine.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
>index a688bb2d96ce..b9c5690c4d96 100644
>--- a/drivers/gpu/drm/xe/xe_hw_engine.c
>+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
>@@ -720,6 +720,11 @@ static void check_gsc_availability(struct xe_gt *gt)
> 	 */
> 	if (!xe_uc_fw_is_available(&gt->uc.gsc.fw)) {
> 		gt->info.engine_mask &= ~BIT(XE_HW_ENGINE_GSCCS0);
>+
>+		/* interrupts where previously enabled, so turn them off */
>+		xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, 0);
>+		xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~0);
>+
> 		drm_info(&xe->drm, "gsccs disabled due to lack of FW\n");
> 	}
> }
>-- 
>2.43.0
>