[PATCH v3 1/7] drm/xe: Introduce has_atomic_enable_pte_bit device info

[Zeng, Oak]

Reviewed-by: Oak Zeng <oak.zeng at intel.com>

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of
> Nirmoy Das
> Sent: Monday, April 15, 2024 10:52 AM
> To: intel-xe at lists.freedesktop.org
> Cc: Das, Nirmoy <nirmoy.das at intel.com>
> Subject: [PATCH v3 1/7] drm/xe: Introduce has_atomic_enable_pte_bit
> device info
> 
> Add has_atomic_enable_pte_bit to specify that a device
> has PTE_AE bit in its PTE feild. Currently XE2 and PVC
> supports this so set this for those two.
> 
> This will help consolidate setting atomic access bit in PTE
> logic which is spread between multiple files.
> 
> Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>  drivers/gpu/drm/xe/xe_pci.c          | 3 +++
>  drivers/gpu/drm/xe/xe_pci_types.h    | 1 +
>  3 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 60ced5f90c2b..bde42fe288ff 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -281,6 +281,8 @@ struct xe_device {
>  		u8 has_heci_gscfi:1;
>  		/** @info.skip_guc_pc: Skip GuC based PM feature init */
>  		u8 skip_guc_pc:1;
> +		/** @info.has_atomic_enable_pte_bit: Device has atomic
> enable PTE bit */
> +		u8 has_atomic_enable_pte_bit:1;
> 
>  #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>  		struct {
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 3b30353dbc09..9cf45559b915 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -146,6 +146,7 @@ static const struct xe_graphics_desc graphics_xehpc =
> {
>  	.vram_flags = XE_VRAM_FLAGS_NEED64K,
> 
>  	.has_asid = 1,
> +	.has_atomic_enable_pte_bit = 1,
>  	.has_flat_ccs = 0,
>  	.has_usm = 1,
>  };
> @@ -163,6 +164,7 @@ static const struct xe_graphics_desc graphics_xelpg =
> {
>  #define XE2_GFX_FEATURES \
>  	.dma_mask_size = 46, \
>  	.has_asid = 1, \
> +	.has_atomic_enable_pte_bit = 1, \
>  	.has_flat_ccs = 1, \
>  	.has_range_tlb_invalidation = 1, \
>  	.has_usm = 1, \
> @@ -627,6 +629,7 @@ static int xe_info_init(struct xe_device *xe,
>  	xe->info.va_bits = graphics_desc->va_bits;
>  	xe->info.vm_max_level = graphics_desc->vm_max_level;
>  	xe->info.has_asid = graphics_desc->has_asid;
> +	xe->info.has_atomic_enable_pte_bit = graphics_desc-
> >has_atomic_enable_pte_bit;
>  	xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
>  	xe->info.has_range_tlb_invalidation = graphics_desc-
> >has_range_tlb_invalidation;
>  	xe->info.has_usm = graphics_desc->has_usm;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> b/drivers/gpu/drm/xe/xe_pci_types.h
> index b1ad12fa22d6..e1f2b4879fc2 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -25,6 +25,7 @@ struct xe_graphics_desc {
>  	u8 max_remote_tiles:2;
> 
>  	u8 has_asid:1;
> +	u8 has_atomic_enable_pte_bit:1;
>  	u8 has_flat_ccs:1;
>  	u8 has_range_tlb_invalidation:1;
>  	u8 has_usm:1;
> --
> 2.42.0