[PATCH 3/5] drm/xe: Add few more GT register definitions

[Piotr Piórkowski]

Michal Wajdeczko <michal.wajdeczko at intel.com> wrote on czw [2024-kwi-18 17:28:00 +0200]:
> While we are not using these registers right now, they are part
> of some runtime register lists that PF driver share with VFs on
> some legacy platforms that we might want to support as SDV.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 94445810ccc9..6eea7a459c68 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -173,8 +173,11 @@
>  #define   MAX_MSLICES				4
>  #define   MEML3_EN_MASK				REG_GENMASK(3, 0)
>  
> +#define MIRROR_FUSE1				XE_REG(0x911c)
> +
>  #define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */
>  #define   XELP_EU_MASK				REG_GENMASK(7, 0)
> +#define XELP_GT_SLICE_ENABLE			XE_REG(0x9138)
>  #define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
>  
>  #define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)


Reviewed-by: Piotr Piórkowski <piotr.piorkowski at intel.com>
> -- 
> 2.43.0
> 

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