✓ CI.checkpatch: success for drm/xe/xe_gt_idle: add debugfs entry for powergating info (rev3)

[Patchwork]

== Series Details ==

Series: drm/xe/xe_gt_idle: add debugfs entry for powergating info (rev3)
URL   : https://patchwork.freedesktop.org/series/136477/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
7b537a014c4c1a32250e342541870b03977fa7a4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 14eb7d626059051684822f76c51e57f846453c10
Author: Riana Tauro <riana.tauro at intel.com>
Date:   Thu Aug 1 15:23:05 2024 +0530

    drm/xe/xe_gt_idle: add debugfs entry for powergating info
    
    Coarse Powergating is a power saving technique where Render and Media
    can be power-gated independently irrespective of the rest of the GT.
    
    For debug purposes, it is useful to expose the powergating information.
    
    v2: move to debugfs
        add details to commit message
        add per-slice status for media
        define reg bits in descending order (Matt Roper)
    
    v3: fix return statement
        fix kernel-doc
        use loop for media slices
        use helper function for status (Michal)
    
    v4: add pg prefix
        do not wake GT if in C6 (Badal)
    
    Signed-off-by: Riana Tauro <riana.tauro at intel.com>
+ /mt/dim checkpatch 8019170840644b0c5a5e64fc6d81792dd2105a2d drm-intel
5fbb7a0c34da drm/xe/xe_gt_idle: store powergate enable bits in gtidle
14eb7d626059 drm/xe/xe_gt_idle: add debugfs entry for powergating info