✓ CI.checkpatch: success for Shuffle MCR init order and use MCR reg

[Patchwork]

== Series Details ==

Series: Shuffle MCR init order and use MCR reg
URL   : https://patchwork.freedesktop.org/series/137018/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
66551fd1be58212fb46d0bc97f2e5ae43c69b733
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 4f4c8d8430fd03e7f109839db099d3e3eb32a346
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date:   Thu Aug 8 11:32:51 2024 +0530

    drm/xe: Init MCR before any mcr register read
    
    enable host l2 RAM is example where MCR register is
    getting read before fully MCR init is done. Lets move
    MCR init early and merge early mcr init into main MCR
    init.
    
    Cc: Lucas De Marchi <lucas.demarchi at intel.com>
    Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch 4f5d551409fb5562ab0d732120e7ac9b698b5864 drm-intel
355d1482c7e4 drm/xe: Write all slices if its mcr register
4f4c8d8430fd drm/xe: Init MCR before any mcr register read