✓ CI.checkpatch: success for Shuffle enable_host_l2_vram order and use MCR reg
Patchwork
patchwork at emeril.freedesktop.org
Thu Aug 8 09:46:48 UTC 2024
== Series Details ==
Series: Shuffle enable_host_l2_vram order and use MCR reg
URL : https://patchwork.freedesktop.org/series/137031/
State : success
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
66551fd1be58212fb46d0bc97f2e5ae43c69b733
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 91b5a461f7faad7f668689f1a163af54726e147f
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date: Thu Aug 8 14:58:26 2024 +0530
drm/xe: Write all slices if its mcr register
Register GAMREQSTRM_CTRL should be considered mcr register
which should write to all slices as per documentation.
Bspec: 71185
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch b6a72e1d0a6ee0aad5bb0da07b050228c815a5f9 drm-intel
a19575677b46 drm/xe: Init MCR before any mcr register read
91b5a461f7fa drm/xe: Write all slices if its mcr register
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