✗ CI.checkpatch: warning for Add HDMI PLL Algorithm for SNPS/C10PHY (rev3)

[Patchwork]

== Series Details ==

Series: Add HDMI PLL Algorithm for SNPS/C10PHY (rev3)
URL   : https://patchwork.freedesktop.org/series/135396/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
9fe5037901cabbcdf27a6fe0dfb047ca1474d363
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 53b47b1b7665a7a6ea701a61328c5c2610894eb5
Author: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
Date:   Tue Aug 13 08:49:38 2024 +0530

    drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY
    
    Try HDMI PLL alogorithm for C10 PHY, if there are no pre-computed tables.
    Also get rid of the helpers to get rate for HDMI for C10/20 PHY, as we no
    longer depend only on pre-computed tables.
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
+ /mt/dim checkpatch bb06cec392c188bc980be5cee9a85240ce866b78 drm-intel
749cb8c72ebb drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2
-:42: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 315 lines checked
65a425592b21 drm/i915/snps_phy: Use HDMI PLL algorithm for DG2
0c53853ab52f drm/i915/cx0_phy_regs: Add C10 registers bits
0a56edbe72fd drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm
53b47b1b7665 drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY