✓ CI.checkpatch: success for Shuffle enable_host_l2_vram order and use MCR reg (rev2)

[Patchwork]

== Series Details ==

Series: Shuffle enable_host_l2_vram order and use MCR reg (rev2)
URL   : https://patchwork.freedesktop.org/series/137031/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
9fe5037901cabbcdf27a6fe0dfb047ca1474d363
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit fabaa8137a98b7f46ee73e3771ba87f80bc64bfd
Author: Tejas Upadhyay <tejas.upadhyay at intel.com>
Date:   Wed Aug 14 15:26:14 2024 +0530

    drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register
    
    Register STATELESS_COMPRESSION_CTRL should be considered
    mcr register which should write to all slices as per
    documentation.
    
    Bspec: 71185
    Fixes: ecabb5e6ce54 ("drm/xe/xe2: Add performance turning changes")
    Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
+ /mt/dim checkpatch 95179e2efd2e2f61d5453d323fdb6e136fc15df6 drm-intel
0bd692707d25 drm/xe: Move enable host l2 VRAM post MCR init
7d7ce663115c drm/xe: Write all slices if its mcr register
fabaa8137a98 drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register