[PATCH V2 3/3] drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register

[Chauhan, Shekhar]

Will get to your other patches soon.

On 8/14/2024 3:26 PM, Tejas Upadhyay wrote:
> Register STATELESS_COMPRESSION_CTRL should be considered
> mcr register which should write to all slices as per
> documentation.
>
> Bspec: 71185
> Fixes: ecabb5e6ce54 ("drm/xe/xe2: Add performance turning changes")
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

LGTM,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan at intel.com>

> ---
>   drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index aeb17fcb27ac..0d1a4a9f4e11 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -80,7 +80,7 @@
>   #define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
>   #define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
>   
> -#define STATELESS_COMPRESSION_CTRL		XE_REG(0x4148)
> +#define STATELESS_COMPRESSION_CTRL		XE_REG_MCR(0x4148)
>   #define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)
>   
>   #define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)

-- 
-shekhar