✓ CI.checkpatch: success for drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates

[Patchwork]

== Series Details ==

Series: drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates
URL   : https://patchwork.freedesktop.org/series/137612/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
9fe5037901cabbcdf27a6fe0dfb047ca1474d363
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1cecd54338bb45f9b6d67fc895f8390fced2ae36
Author: Chaitanya Kumar Borah <chaitanya.kumar.borah at intel.com>
Date:   Thu Aug 22 11:44:48 2024 +0530

    drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates
    
    In case of UHBR rates, we do not need to explicitly enable FEC by writing
    to DP_TP_CTL register.
    For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of
    setting fec_enable to false. However, it gets overwritten in
    intel_dp_dsc_compute_config(). This change keeps fec_enable false across
    MST and SST use-cases for UHBR rates.
    
    While at it, add a comment explaining why we don't enable FEC in eDP v1.5.
    
    v2: Correct logic to cater to SST use-cases (Jani)
    
    Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah at intel.com>
+ /mt/dim checkpatch 4c294bd7d8c84305dbb1de1aa9e010818e3f4b7e drm-intel
1cecd54338bb drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates