[PATCH 3/5] drm/xe: add memirq offsets for engine instance 0 to hw engine properties
Cavitt, Jonathan
jonathan.cavitt at intel.com
Mon Aug 26 15:06:41 UTC 2024
-----Original Message-----
From: Ilia Levi <illevi at habana.ai>
Sent: Monday, August 26, 2024 6:32 AM
To: Cavitt, Jonathan <jonathan.cavitt at intel.com>; Levi, Ilia <ilia.levi at intel.com>; intel-xe at lists.freedesktop.org
Cc: Wajdeczko, Michal <Michal.Wajdeczko at intel.com>; Vishwanathapura, Niranjana <niranjana.vishwanathapura at intel.com>; Elbaz, Koby <koby.elbaz at intel.com>; Avizrat, Yaron <yaron.avizrat at intel.com>
Subject: Re: [PATCH 3/5] drm/xe: add memirq offsets for engine instance 0 to hw engine properties
>
> On 8/22/24 18:42, Cavitt, Jonathan wrote:
> > -----Original Message-----
> > From: Intel-xe<intel-xe-bounces at lists.freedesktop.org> On Behalf Of Ilia Levi
> > Sent: Thursday, August 22, 2024 6:08 AM
> > To:intel-xe at lists.freedesktop.org
> > Cc: Levi, Ilia<ilia.levi at intel.com>; Wajdeczko, Michal<Michal.Wajdeczko at intel.com>; Vishwanathapura, Niranjana<niranjana.vishwanathapura at intel.com>; Elbaz, Koby<koby.elbaz at intel.com>; Avizrat, Yaron<yaron.avizrat at intel.com>
> > Subject: [PATCH 3/5] drm/xe: add memirq offsets for engine instance 0 to hw engine properties
> >> This is needed for accessing memirq interrupt status and source for
> >> MSI-X devices.
> >>
> >> Signed-off-by: Ilia Levi<ilia.levi at intel.com>
> > Here are two alternative solutions to consider:
> >
> > 1.
> > Create a function that takes a hwe and returns the e0_irq_offset from the
> > engine class:
> >
> > """
> > static inline int xe_hw_engine_get_e0_irq_offset(struct xe_hw_engine *hwe)
> > {
> > switch (hwe->class) {
> > case XE_ENGINE_CLASS_RENDER:
> > return ilog2(INTR_RCS0);
> > case XE_ENGINE_CLASS_COPY:
> > return ilog2(INTR_BCS(0));
> > case XE_ENGINE_CLASS_VIDEO_DECODE:
> > return ilog2(INTR_VCS(0));
> > case XE_ENGINE_CLASS_VIDEO_ENHANCE:
> > return ilog2(INTR_VECS(0));
> > case XE_ENGINE_CLASS_COMPUTE:
> > return ilog2(INTR_CCS(0));
> > default:
> > return -EINVAL;
> > }
> > }
> > """
> >
> > 2.
> > Same as above, but with a dictionary:
> >
> > """
> > static const int e0_irq_offset[] = {
> > [XE_ENGINE_CLASS_RENDER] = ilog2(INTR_RCS0),
> > [XE_ENGINE_CLASS_COPY] = ilog2(INTR_BCS(0)),
> > [XE_ENGINE_CLASS_VIDEO_DECODE] = ilog2(INTR_VCS(0)),
> > [XE_ENGINE_CLASS_VIDEO_ENHANCE] = ilog2(INTR_VECS(0)),
> > [XE_ENGINE_CLASS_COMPUTE] = ilog2(INTR_CCS(0)),
> > };
> > """
> >
> > I put both of these into xe_hw_engine.h to assure the formatting was correct,
> > and I should note that wherever these functions are put, you'll need to include
> > "regs/xe_gt_regs.h".
> >
> > Also, note that in the case of the second solution, you may need to squash
> > this patch into the next one to prevent "unused variable" warnings on
> > compilation.
> >
> >
> > I have no problems with the current implementation, and thus won't block
> > on these considerations, but someone else might want one of these solutions
> > instead.
> >
> > Reviewed-by: Jonathan Cavitt<jonathan.cavitt at intel.com>
> > -Jonathan Cavitt
> >
> Since this code is used by the interrupt handler (xe_memirq_hwe_handler
> in the subsequent patch),
> I feel like performance-wise it would be more efficient to pre-compute
> the value for each engine without switching/hopping by engine class.
>
> I could use your solution during initialization phase, e.g. something like:
> """
> hwe->e0_irq_offset = get_e0_irq_offset_from_class(hwe->class);
> """
> Instead of
> """
> hwe->e0_irq_offset = info->e0_irq_offset;
> """
>
> And then get_e0_irq_offset_from_class can be static inside the
> xe_hw_engine.c file.
> I don't have a strong preference either way, especially since we already
> use 32 bits in struct engine_info, but let me know if you think it makes
> sense to change the code.
I don't have a strong preference either, and recommend getting a second
opinion on the matter. My Reviewed-by still stands, regardless of what
option is chosen.
-Jonathan Cavitt
>
> Ilia
> >> ---
> >> drivers/gpu/drm/xe/xe_hw_engine.c | 28 +++++++++++++++++++++++++
> >> drivers/gpu/drm/xe/xe_hw_engine_types.h | 2 ++
> >> 2 files changed, 30 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> >> index aa9b2b16a6e0..b73a4379ce06 100644
> >> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> >> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> >> @@ -44,6 +44,7 @@ struct engine_info {
> >> unsigned int class : 8;
> >> unsigned int instance : 8;
> >> unsigned int irq_offset : 8;
> >> + unsigned int e0_irq_offset : 8;
> >> enum xe_force_wake_domains domain;
> >> u32 mmio_base;
> >> };
> >> @@ -54,6 +55,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_RENDER,
> >> .instance = 0,
> >> .irq_offset = ilog2(INTR_RCS0),
> >> + .e0_irq_offset = ilog2(INTR_RCS0),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = RENDER_RING_BASE,
> >> },
> >> @@ -62,6 +64,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 0,
> >> .irq_offset = ilog2(INTR_BCS(0)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = BLT_RING_BASE,
> >> },
> >> @@ -70,6 +73,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 1,
> >> .irq_offset = ilog2(INTR_BCS(1)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS1_RING_BASE,
> >> },
> >> @@ -78,6 +82,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 2,
> >> .irq_offset = ilog2(INTR_BCS(2)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS2_RING_BASE,
> >> },
> >> @@ -86,6 +91,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 3,
> >> .irq_offset = ilog2(INTR_BCS(3)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS3_RING_BASE,
> >> },
> >> @@ -94,6 +100,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 4,
> >> .irq_offset = ilog2(INTR_BCS(4)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS4_RING_BASE,
> >> },
> >> @@ -102,6 +109,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 5,
> >> .irq_offset = ilog2(INTR_BCS(5)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS5_RING_BASE,
> >> },
> >> @@ -110,6 +118,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 6,
> >> .irq_offset = ilog2(INTR_BCS(6)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS6_RING_BASE,
> >> },
> >> @@ -117,6 +126,7 @@ static const struct engine_info engine_infos[] = {
> >> .name = "bcs7",
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .irq_offset = ilog2(INTR_BCS(7)),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .instance = 7,
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS7_RING_BASE,
> >> @@ -126,6 +136,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COPY,
> >> .instance = 8,
> >> .irq_offset = ilog2(INTR_BCS8),
> >> + .e0_irq_offset = ilog2(INTR_BCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = XEHPC_BCS8_RING_BASE,
> >> },
> >> @@ -135,6 +146,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 0,
> >> .irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX0,
> >> .mmio_base = BSD_RING_BASE,
> >> },
> >> @@ -143,6 +155,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 1,
> >> .irq_offset = 32 + ilog2(INTR_VCS(1)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX1,
> >> .mmio_base = BSD2_RING_BASE,
> >> },
> >> @@ -151,6 +164,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 2,
> >> .irq_offset = 32 + ilog2(INTR_VCS(2)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX2,
> >> .mmio_base = BSD3_RING_BASE,
> >> },
> >> @@ -159,6 +173,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 3,
> >> .irq_offset = 32 + ilog2(INTR_VCS(3)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX3,
> >> .mmio_base = BSD4_RING_BASE,
> >> },
> >> @@ -167,6 +182,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 4,
> >> .irq_offset = 32 + ilog2(INTR_VCS(4)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX4,
> >> .mmio_base = XEHP_BSD5_RING_BASE,
> >> },
> >> @@ -175,6 +191,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 5,
> >> .irq_offset = 32 + ilog2(INTR_VCS(5)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX5,
> >> .mmio_base = XEHP_BSD6_RING_BASE,
> >> },
> >> @@ -183,6 +200,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 6,
> >> .irq_offset = 32 + ilog2(INTR_VCS(6)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX6,
> >> .mmio_base = XEHP_BSD7_RING_BASE,
> >> },
> >> @@ -191,6 +209,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_DECODE,
> >> .instance = 7,
> >> .irq_offset = 32 + ilog2(INTR_VCS(7)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VCS(0)),
> >> .domain = XE_FW_MEDIA_VDBOX7,
> >> .mmio_base = XEHP_BSD8_RING_BASE,
> >> },
> >> @@ -199,6 +218,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> >> .instance = 0,
> >> .irq_offset = 32 + ilog2(INTR_VECS(0)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VECS(0)),
> >> .domain = XE_FW_MEDIA_VEBOX0,
> >> .mmio_base = VEBOX_RING_BASE,
> >> },
> >> @@ -207,6 +227,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> >> .instance = 1,
> >> .irq_offset = 32 + ilog2(INTR_VECS(1)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VECS(0)),
> >> .domain = XE_FW_MEDIA_VEBOX1,
> >> .mmio_base = VEBOX2_RING_BASE,
> >> },
> >> @@ -215,6 +236,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> >> .instance = 2,
> >> .irq_offset = 32 + ilog2(INTR_VECS(2)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VECS(0)),
> >> .domain = XE_FW_MEDIA_VEBOX2,
> >> .mmio_base = XEHP_VEBOX3_RING_BASE,
> >> },
> >> @@ -223,6 +245,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_VIDEO_ENHANCE,
> >> .instance = 3,
> >> .irq_offset = 32 + ilog2(INTR_VECS(3)),
> >> + .e0_irq_offset = 32 + ilog2(INTR_VECS(0)),
> >> .domain = XE_FW_MEDIA_VEBOX3,
> >> .mmio_base = XEHP_VEBOX4_RING_BASE,
> >> },
> >> @@ -231,6 +254,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COMPUTE,
> >> .instance = 0,
> >> .irq_offset = ilog2(INTR_CCS(0)),
> >> + .e0_irq_offset = ilog2(INTR_CCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = COMPUTE0_RING_BASE,
> >> },
> >> @@ -239,6 +263,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COMPUTE,
> >> .instance = 1,
> >> .irq_offset = ilog2(INTR_CCS(1)),
> >> + .e0_irq_offset = ilog2(INTR_CCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = COMPUTE1_RING_BASE,
> >> },
> >> @@ -247,6 +272,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COMPUTE,
> >> .instance = 2,
> >> .irq_offset = ilog2(INTR_CCS(2)),
> >> + .e0_irq_offset = ilog2(INTR_CCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = COMPUTE2_RING_BASE,
> >> },
> >> @@ -255,6 +281,7 @@ static const struct engine_info engine_infos[] = {
> >> .class = XE_ENGINE_CLASS_COMPUTE,
> >> .instance = 3,
> >> .irq_offset = ilog2(INTR_CCS(3)),
> >> + .e0_irq_offset = ilog2(INTR_CCS(0)),
> >> .domain = XE_FW_RENDER,
> >> .mmio_base = COMPUTE3_RING_BASE,
> >> },
> >> @@ -481,6 +508,7 @@ static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
> >> hwe->instance = info->instance;
> >> hwe->mmio_base = info->mmio_base;
> >> hwe->irq_offset = info->irq_offset;
> >> + hwe->e0_irq_offset = info->e0_irq_offset;
> >> hwe->domain = info->domain;
> >> hwe->name = info->name;
> >> hwe->fence_irq = >->fence_irq[info->class];
> >> diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> >> index 39f24012d0f4..18998e204458 100644
> >> --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> >> +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> >> @@ -118,6 +118,8 @@ struct xe_hw_engine {
> >> u16 logical_instance;
> >> /** @irq_offset: IRQ offset of this hw engine */
> >> u16 irq_offset;
> >> + /** @e0_irq_offset: IRQ offset of engine instance 0 (of that class) */
> >> + u16 e0_irq_offset;
> >> /** @mmio_base: MMIO base address of this hw engine*/
> >> u32 mmio_base;
> >> /**
> >> --
> >> 2.43.2
> >>
> >>
>
>
>
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