[PATCH] drm/i915/cx0: split out mtl_get_cx0_buf_trans() to c10 and c20 variants

[Kahola, Mika]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula at intel.com>
> Sent: Friday, 29 November 2024 13.42
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula at intel.com>; Kahola, Mika <mika.kahola at intel.com>
> Subject: [PATCH] drm/i915/cx0: split out mtl_get_cx0_buf_trans() to c10 and c20
> variants
> 
> The PHY is either c10 or c20, there's no need to check at runtime and complicate
> the conditions in mtl_get_cx0_buf_trans().
> 
> While at it, replace the direct port clock check with intel_dp_is_uhbr().
> 
> Cc: Mika Kahola <mika.kahola at intel.com>

The change is reasonable and solid.

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  .../drm/i915/display/intel_ddi_buf_trans.c    | 23 +++++++++++++------
>  1 file changed, 16 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 4d21ce734343..9389b295036e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1687,18 +1687,24 @@ dg2_get_snps_buf_trans(struct intel_encoder
> *encoder,  }
> 
>  static const struct intel_ddi_buf_trans * -mtl_get_cx0_buf_trans(struct
> intel_encoder *encoder,
> +mtl_get_c10_buf_trans(struct intel_encoder *encoder,
>  		      const struct intel_crtc_state *crtc_state,
>  		      int *n_entries)
>  {
> -	if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >=
> 1000000)
> +	return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries); }
> +
> +static const struct intel_ddi_buf_trans * mtl_get_c20_buf_trans(struct
> +intel_encoder *encoder,
> +		      const struct intel_crtc_state *crtc_state,
> +		      int *n_entries)
> +{
> +	if (intel_crtc_has_dp_encoder(crtc_state) &&
> +intel_dp_is_uhbr(crtc_state))
>  		return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
> -	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> !(intel_encoder_is_c10phy(encoder)))
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
> -	else if (!intel_encoder_is_c10phy(encoder))
> -		return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
>  	else
> -		return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries);
> +		return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
>  }
> 
>  void intel_ddi_buf_trans_init(struct intel_encoder *encoder) @@ -1706,7
> +1712,10 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> 
>  	if (DISPLAY_VER(i915) >= 14) {
> -		encoder->get_buf_trans = mtl_get_cx0_buf_trans;
> +		if (intel_encoder_is_c10phy(encoder))
> +			encoder->get_buf_trans = mtl_get_c10_buf_trans;
> +		else
> +			encoder->get_buf_trans = mtl_get_c20_buf_trans;
>  	} else if (IS_DG2(i915)) {
>  		encoder->get_buf_trans = dg2_get_snps_buf_trans;
>  	} else if (IS_ALDERLAKE_P(i915)) {
> --
> 2.39.5