✓ CI.checkpatch: success for reg_sr/whitelist fixes and refactors (rev2)

[Patchwork]

== Series Details ==

Series: reg_sr/whitelist fixes and refactors (rev2)
URL   : https://patchwork.freedesktop.org/series/142195/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1df3f61cedb7bf72904716f9850454acb8b98396
Author: Lucas De Marchi <lucas.demarchi at intel.com>
Date:   Mon Dec 9 15:27:39 2024 -0800

    drm/xe: Apply whitelist to engine save-restore
    
    Instead of handling the whitelist directly in the GuC ADS
    initialization, make it follow the same logic as other engine registers
    that are save-restored. Main benefit is that then the SW tracking then
    shows it in debugfs and there's no risk of an engine workaround to write
    to the same nopriv register that is being passed directly to GuC.
    
    This means that xe_reg_whitelist_process_engine() only has to process
    the RTP and convert them to entries for the hwe.  With that all the
    registers should be covered by xe_reg_sr_apply_mmio() to write to the HW
    and there's no special handling in GuC ADS to also add these registers
    to the list of registers that is passed to GuC.
    
    Example for DG2:
    
            # cat  /sys/kernel/debug/dri/0000\:03\:00.0/gt0/register-save-restore
            ...
            Engine
            rcs0
                    ...
                    REG[0x24d0] clr=0xffffffff set=0x1000dafc masked=no mcr=no
                    REG[0x24d4] clr=0xffffffff set=0x1000db01 masked=no mcr=no
                    REG[0x24d8] clr=0xffffffff set=0x0000db1c masked=no mcr=no
            ...
            Whitelist
            rcs0
                    REG[0xdafc-0xdaff]: allow read access
                    REG[0xdb00-0xdb1f]: allow read access
                    REG[0xdb1c-0xdb1f]: allow rw access
    
    v2:
      - Use ~0u for clr bits so it's just a write (Matt Roper)
      - Simplify helpers now that unused slots are not written
    
    Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
+ /mt/dim checkpatch 9d12021e081c72b18c31bda175fb9a43f1d005fc drm-intel
d34d6936d35c drm/xe/reg_sr: Remove register pool
fc4e15c17fd3 drm/xe: Introduce xe_gt_dbg_printer()
40d6a7a793ab drm/xe/reg_sr: Convert whitelist to gt logging
6face06f66e6 drm/xe/reg_sr: Stop setting all whitelist slots
1df3f61cedb7 drm/xe: Apply whitelist to engine save-restore