[PATCH] drm/xe/ptl: Apply Wa_14023061436

[Matt Roper]

On Tue, Dec 10, 2024 at 04:06:21PM +0100, Nirmoy Das wrote:
> Enable WMTP for the BTD kernel to address Wa14023061436 by setting the
> proper TDL Chicken Bit.
> 
> Cc: Gustavo Sousa <gustavo.sousa at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
>  drivers/gpu/drm/xe/xe_wa.c           | 4 ++++
>  2 files changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 162f18e975da..6829fbed1803 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -496,6 +496,9 @@
>  #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
>  #define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
>  
> +#define TDL_CHICKEN				XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
> +#define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE	REG_BIT(12)

e5f4 > e5f0 so I think this needs to be after the XEHP_HDC_CHICKEN0
definition.


> +
>  #define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
>  #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
>  #define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 570fe0376402..2889d6f65f51 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -637,6 +637,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {

I don't see this register in the RCS engine's LRC (bspec 65182), so I'm
not sure this is the correct list.  We probably need this on
engine_was[] so that this will be saved/restored properly around engine
resets.

>  	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
>  	  XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC))
>  	},
> +	{ XE_RTP_NAME("14023061436"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), ENGINE_CLASS(RENDER)),

Given the above (that this isn't tied to one specific engine's LRC) and
given that the register doesn't fall within the dedicated RCS range
(0x2xxx), we should probably also change the ENGINE_CLASS(RENDER) to
FUNC(xe_rtp_match_first_render_or_compute) here.  For PTL (the only
platform that uses these IPs at the moment) it doesn't really matter,
but if we wind up extending this to some other platform in the future
that lacks an RCS, then using the 'first render or compute' match will
ensure that the workaround still gets applied properly in the absence of
an RCS engine.


Matt

> +	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE))
> +	},
>  
>  	/* DG1 */
>  
> -- 
> 2.46.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation