[PATCH] drm/xe/guc: Enable WA_DUAL_QUEUE for newer platforms

[Cavitt, Jonathan]

-----Original Message-----
From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Daniele Ceraolo Spurio
Sent: Tuesday, November 26, 2024 5:11 PM
To: intel-xe at lists.freedesktop.org
Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio at intel.com>; Harrison, John C <john.c.harrison at intel.com>
Subject: [PATCH] drm/xe/guc: Enable WA_DUAL_QUEUE for newer platforms
> 
> The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions
> on RCS and CCSes with different address spaces, which on DG2 is
> required as a WA for an HW bug. On newer platforms, this block has
> been moved in HW at the CS level, by stalling the RCS/CCS context
> switch when one of the other RCS/CCSes is busy with a different
> address space. While functionally correct, having a submission
> stalled on the HW limits the GuC ability to shuffle things around and
> can cause complications if the non-stalled submission runs for a long
> time, because the GuC doesn't know that the stalled submission isn't
> actually running and might declare it as hung. Therefore, we enable
> the DUAL_QUEUE_WA on all newer platforms to move management back to
> the GuC.
> 
> Note that the GuC specs also recommend enabling this for all platforms
> starting from MTL that have a CCS.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: John Harrison <John.C.Harrison at Intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index df1ba94cf4ca..ddbfbdf901b0 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -151,7 +151,21 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
>  	if (XE_WA(gt, 14014475959))
>  		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>  
> -	if (XE_WA(gt, 22011391025))
> +	/*
> +	 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions
> +	 * on RCS and CCSes with different address spaces, which on DG2 is
> +	 * required as a WA for an HW bug. On newer platforms, this block has
> +	 * been moved in HW at the CS level, by stalling the RCS/CCS context
> +	 * switch when one of the other RCS/CCSes is busy with a different
> +	 * address space. While functionally correct, having a submission
> +	 * stalled on the HW limits the GuC ability to shuffle things around and
> +	 * can cause complications if the non-stalled submission runs for a long
> +	 * time, because the GuC doesn't know that the stalled submission isn't
> +	 * actually running and might declare it as hung. Therefore, we enable
> +	 * the DUAL_QUEUE_WA on all newer platforms to move management back to
> +	 * the GuC.
> +	 */
> +	if (XE_WA(gt, 22011391025) || GRAPHICS_VERx100(xe) >= 1270)

This is acceptable, and preliminary testing shows that this fix will repair
several observed issues.  Though I'm a bit confused why we aren't adding
the additional graphics version check to the workaround itself?

Is it because the workaround implies a hardware problem, whereas the
additional applications we're applying it to here are not related to hardware-
specific limitations/issues?  I think it's a bit odd to make such a distinction,
but that's just my opinion I won't block on it.

Regardless of if we decide to keep this implementation or merge the check into
xe_wa_oob.rules:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>

By the way, this patch was also separately reviewed by Jesus Narvaez, so
don't forget to add their RB in as well.
-Jonathan Cavitt

>  		flags |= GUC_WA_DUAL_QUEUE;
>  
>  	/*
> -- 
> 2.43.0
> 
>