[PATCH] drm/xe: Mark ComputeCS read mode as UC on iGPU

[Matthew Brost]

RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
structure. Having this as WB blocks ULLS from being enabled. Change to
UC to unblock ULLS on iGPU.

Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
Cc: Michal Mrozek <michal.mrozek at intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
Cc: José Roberto de Souza <jose.souza at intel.com>
Cc: stable at vger.kernel.org
Fixes: 328e089bfb37 ("drm/xe: Leverage ComputeCS read L3 caching")
Signed-off-by: Matthew Brost <matthew.brost at intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index b19366744148..cc258b2a77c9 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -417,9 +417,14 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 	 * entry is recommended by the spec in certain circumstances on
 	 * specific platforms.
 	 * Bspec: 72161
+	 *
+	 * XXX: According to internal communications bspec is wrong and
+	 * RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
+	 * structure. Having this as WB blocks ULLS from being enabled. Add
+	 * bspec link or delete this comment once bspec is updated.
 	 */
 	const u8 mocs_write_idx = gt->mocs.uc_index;
-	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE &&
+	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
 				 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
 				 gt->mocs.wb_index : gt->mocs.uc_index;
 	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
-- 
2.34.1