✗ CI.checkpatch: warning for drm/i915/display: UHBR rates for Thunderbolt

[Patchwork]

== Series Details ==

Series: drm/i915/display: UHBR rates for Thunderbolt
URL   : https://patchwork.freedesktop.org/series/142649/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 10b0639b4f4ee89716d35a25fd34f6b73b5f8a9c
Author: Mika Kahola <mika.kahola at intel.com>
Date:   Mon Dec 16 14:44:22 2024 +0200

    drm/i915/display: UHBR rates for Thunderbolt
    
    tbt-alt mode is missing uhbr rates 10G and 20G. This requires
    requires pll clock rates 312.5 MHz and 625 MHz to be added,
    respectively. The uhbr rates are supported only form PTL+
    platforms.
    
    Signed-off-by: Mika Kahola <mika.kahola at intel.com>
+ /mt/dim checkpatch 6ef018c1fd86cf86387e2175edf76476cb144095 drm-intel
10b0639b4f4e drm/i915/display: UHBR rates for Thunderbolt
-:89: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#89: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:192:
+#define   XE3LPDP_DDI_CLOCK_SELECT(val)			REG_FIELD_PREP(XE3LPDP_DDI_CLOCK_SELECT_MASK, val)

total: 0 errors, 1 warnings, 0 checks, 75 lines checked