✓ CI.checkpatch: success for drm/i915/cx0_phy: Fix C10 pll programming sequence

[Patchwork]

== Series Details ==

Series: drm/i915/cx0_phy: Fix C10 pll programming sequence
URL   : https://patchwork.freedesktop.org/series/142670/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 29853f078998a7936035348b622cf8d3956c0234
Author: Suraj Kandpal <suraj.kandpal at intel.com>
Date:   Mon Dec 16 23:45:54 2024 +0530

    drm/i915/cx0_phy: Fix C10 pll programming sequence
    
    According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
    specific VDR registers and TX Lane programming registers are done.
    Moreover we only program into C10_VDR_CONTROL1 to update config and
    setup master lane once all VDR registers are written into.
    Bspec: 67636
    
    Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming")
    Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
+ /mt/dim checkpatch 49cc582754c205bbe43d4ef2b1fd3894bee1f3bd drm-intel
29853f078998 drm/i915/cx0_phy: Fix C10 pll programming sequence