[PATCH] drm/xe/dg1: Fix power gate sequence.

[Ghimiray, Himal Prasad]

On 20-12-2024 05:25, Rodrigo Vivi wrote:
> sub-pipe PG is not present on DG1. Setting these bits can disable
> other power gates and cause GPU hangs on video playbacks.
> 
> VLK: 16314, 4304
> 
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
> Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>   drivers/gpu/drm/xe/xe_gt_idle.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_idle.c b/drivers/gpu/drm/xe/xe_gt_idle.c
> index fd80afeef56a..ffd3ba7f6656 100644
> --- a/drivers/gpu/drm/xe/xe_gt_idle.c
> +++ b/drivers/gpu/drm/xe/xe_gt_idle.c
> @@ -122,10 +122,12 @@ void xe_gt_idle_enable_pg(struct xe_gt *gt)
>   	if (!xe_gt_is_media_type(gt))
>   		gtidle->powergate_enable |= RENDER_POWERGATE_ENABLE;
>   
> -	for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
> -		if ((gt->info.engine_mask & BIT(i)))
> -			gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |
> -						     VDN_MFXVDENC_POWERGATE_ENABLE(j));
> +	if (xe->info.platform != XE_DG1) {
> +		for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
> +			if ((gt->info.engine_mask & BIT(i)))
> +				gtidle->powergate_enable |= (VDN_HCP_POWERGATE_ENABLE(j) |
> +							     VDN_MFXVDENC_POWERGATE_ENABLE(j));
> +		}

Looks good to me.
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>

>   	}
>   
>   	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);