[PATCH 04/10] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers

[Ville Syrjälä]

On Fri, Dec 13, 2024 at 08:35:22AM +0200, Jouni Högander wrote:
> Add register definitions for SFF_CTL and CFF_CTL registers. Name them as
> LNL_SFF_CTL and LNL_CFF_CTL.
> 
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 9ad7611506e8..a24f4d76c98a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -251,6 +251,14 @@
>  #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME		REG_BIT(14)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(13)
>  
> +#define _LNL_SFF_CTL_A						0x60918
> +#define LNL_SFF_CTL(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _LNL_SFF_CTL_A)

I don't think we have any funky offset transcoders on new
hardware do we? In that case you can just use the simpler
_MMIO_TRANS().

> +#define  LNL_SFF_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(1)
> +
> +#define _LNL_CFF_CTL_A						0x6091c
> +#define LNL_CFF_CTL(dev_priv, tran)				_MMIO_TRANS2(dev_priv, tran, _LNL_CFF_CTL_A)
> +#define  LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME			REG_BIT(1)
> +
>  /* PSR2 Early transport */
>  #define _PIPE_SRCSZ_ERLY_TPT_A	0x70074
>  #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
> -- 
> 2.34.1

-- 
Ville Syrjälä
Intel