✓ CI.checkpatch: success for series starting with [1/2] drm/xe: Introduce GuC PC debugfs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/xe: Introduce GuC PC debugfs
URL   : https://patchwork.freedesktop.org/series/142885/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 32d15f57f1fd060e4677e7f0b88a389cc4161cc4
Author: Rodrigo Vivi <rodrigo.vivi at intel.com>
Date:   Fri Dec 20 10:30:10 2024 -0500

    drm/xe/lnl: Enable GuC SLPC DCC task
    
    Enable DCC (Duty Cycle Control) in Lunar Lake.
    
    DCC is the SLPC task that tries to keep
    the GT from operating inefficiently when thermally constrained.
    
    Although the recommendation is to enable it, LNL GuC is leaving
    it disabled by default on LNL.
    
    It would minimize the GT frequency oscilation on throttled
    scenarios, what could potentially reduce latencies.
    
    v2: Move set_policies call after wait for running state, so
        we ensure it is not overwritten. (Vinay)
    
    Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
    Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
    Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
+ /mt/dim checkpatch d574310669011e7ef8da6d7e17a2938cae06e077 drm-intel
1dfe0784ea24 drm/xe: Introduce GuC PC debugfs
32d15f57f1fd drm/xe/lnl: Enable GuC SLPC DCC task