✓ CI.checkpatch: success for series starting with [1/2] drm/xe: Introduce GuC PC debugfs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/xe: Introduce GuC PC debugfs
URL   : https://patchwork.freedesktop.org/series/142894/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 534b1d64e3d4d84b5a650db9169de1628cae296e
Author: Rodrigo Vivi <rodrigo.vivi at intel.com>
Date:   Fri Dec 20 16:41:39 2024 -0500

    drm/xe/lnl: Enable GuC SLPC DCC task
    
    Enable DCC (Duty Cycle Control) in Lunar Lake.
    
    DCC is the SLPC task that tries to keep
    the GT from operating inefficiently when thermally constrained.
    
    Although the recommendation is to enable it, LNL GuC is leaving
    it disabled by default on LNL.
    
    It would minimize the GT frequency oscillation on throttled
    scenarios, which could potentially reduce latencies.
    
    v2: Move set_policies call after wait for running state, so
        we ensure it is not overwritten. (Vinay)
    v3: Fix English in the commit message (Jonathan)
    
    Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
    Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
    Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
+ /mt/dim checkpatch 0eede13975362b755a208b2e2ba322940013f183 drm-intel
c61dc374e14d drm/xe: Introduce GuC PC debugfs
534b1d64e3d4 drm/xe/lnl: Enable GuC SLPC DCC task